Method and apparatus for implementing memory enabled systems using master-slave architecture
View Patent ↗Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
1. A system, comprising:
a memory controller configured to output commands, addresses, and data;
a first memory device configured to:
decode the commands, thereby providing the decoded commands,
latch the addresses and the data from the memory controller via a first port of the first memory device, thereby providing latched addresses and latched data, and
output the decoded commands, the latched addresses, and the latched data via a second port of the first memory device; and
a second memory device comprising a first port and a second port, wherein the second memory device is configured to receive the decoded commands, the latched addresses, and the latched data via the second port of the second memory device,
wherein the first memory device and the second memory device are fabricated using substantially the same fabrication procedures and contain identical components, and
wherein the second memory device includes logic for decoding the commands and the logic is bypassed when the decoded commands, the latched addresses, and the latched data are received via the second port of the second memory device.
2. A system, comprising:
a memory controller configured to output commands, addresses, and data;
a first memory device configured to:
decode the commands, thereby providing the decoded commands,
latch the addresses and the data from the memory controller via a first port of the first memory device, thereby providing latched addresses and latched data and
output the decoded commands, the latched addresses, and the latched
data via a second port of the first memory device; and
a second memory device comprising a first port and a second port, wherein the second memory device is configured to receive the decoded commands, the latched addresses, and the latched data via the second port of the second memory device,
wherein the first memory device comprises a bond pad connected to a first voltage, wherein connecting the bond pad of the first memory device to the first voltage configures the first memory device to decode the commands and latch the addresses and the data from the memory controller; and
wherein the second memory device comprises a bond pad connected to a second voltage, wherein connecting the bond pad of the second memory device to the second voltage configures the second memory device to receive the decoded commands, the latched addresses and the latched data via the second port of the second memory device.
3. A method for operating a system including a first memory device, comprising:
receiving commands, addresses, and data from a memory controller via a first port;
decoding the commands from the memory controller to produce decoded commands;
latching the addresses and the data from the memory controller to produce latched addresses and latched data; and
outputting the decoded commands, the latched addresses, and the latched data to a second memory device via a second port,
wherein outputting the decoded commands, the latched addresses, and the latched data to the second memory device via the second port bypasses logic of the second device for decoding the commands.
4. A memory device, comprising:
a first port;
a second port; and
circuitry configured to place the memory device in at least one of a first mode and a second mode, wherein in the first mode the memory device is configured to:
receive commands, addresses, and data from a memory controller via the first port,
decode the commands from the memory controller to produce decoded commands,
latch the addresses and the data from the memory controller to produce latched addresses and latched data, and
output the decoded commands, the latched addresses, and the latched data to a second memory device via the second port; and
wherein, in the second mode, the memory device is configured to receive decoded commands, latched addresses, and latched data from another memory device via the second port, and wherein, in the second mode, logic for decoding the commands is bypassed when the decoded commands, the latched addresses, and the latched data are received via the second port.
5. A memory device, comprising:
a first port;
a second port; and
circuitry configured to place the memory device in at least one of a first mode and a second mode, wherein in the first mode the memory device is configured to:
receive commands, addresses, and data from a memory controller via the first port,
decode the commands from the memory controller to produce decoded commands,
latch the addresses and the data from the memory controller to produce latched addresses and latched data, and
output the decoded commands, the latched addresses, and the latched data to a second memory device via the second port; and
wherein, in the second mode, the memory device is configured to receive decoded commands, latched addresses, and latched data from another memory device via the second port,
wherein the circuitry comprises a bond pad, and wherein connecting the bond pad to a first voltage places the memory device in the first mode and connecting the bond pad to a second voltage places the memory device in the second mode.