Integrated circuit and method of manufacturing an integrated circuit
View Patent ↗An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
1. A method of manufacturing an integrated circuit including a memory device, comprising
defining an array portion comprising forming memory cells and forming conductive lines, and
defining a support portion comprising forming transistors of a first type, wherein forming the conductive lines comprises defining grooves in a semiconductor substrate and filling the grooves with a conductive material, and wherein forming transistors of the first type comprises defining vertical portions that are vertically adjacent to a channel of the transistor of the first type.
2. The method of claim 1 , further comprising recessing a substrate portion adjacent to the vertical portions.
3. The method of claim 2 , wherein defining the vertical portions is accomplished before recessing the substrate portion.
4. The method of claim 1 , wherein defining the vertical portions comprises etching the semiconductor substrate.
5. The method of claim 1 , wherein defining the vertical portions comprises etching an insulating material that is disposed in isolation trenches that are adjacent to the semiconductor substrate.
6. The method of claim 1 , further comprising defining isolation trenches that are adjacent to the semiconductor substrate, wherein the vertical portions are defined in a self-aligned manner with respect to the position of the isolation trenches.
7. The method of claim 6 , wherein after defining the isolation trenches part of a material filling the isolation trenches protrudes from the isolation trenches, wherein defining the vertical portions comprises providing spacers of a sacrificial material adjacent to the protruding material.
8. The method of claim 7 , wherein the sacrificial material is silicon nitride.
9. The method of claim 1 , wherein providing the memory cells comprises providing transistors of a second type, comprising providing a second gate electrode, wherein providing the second gate electrode comprises defining a gate groove in the semiconductor substrate.
10. The method of claim 1 , further comprising providing a planar transistor comprising a gate electrode which is formed above the semiconductor substrate.