Memory cell with trigger element

1. A memory device, comprising:

a memory cell coupled between a word line and a bit line, the memory cell comprising a memory element selectively coupled to the bit line via a trigger element, wherein the trigger element comprises a thyristor coupled to the word line.

2. The memory device of claim 1 , wherein the thyristor is configured to couple the memory element to the bit line upon application of a pulse to a gate thereof via the respective word line, wherein a duration of the pulse is less than a duration of an access of the memory cell.

3. The memory device of claim 1 , wherein the thyristor is configured to couple the memory element to the bit line upon application of a pulse to a gate thereof via the respective word line, wherein a duration of the pulse is equal to the access of the memory cell.

4. The memory device of claim 1 , wherein the thyristor is configured to couple the memory element to the bit line upon application of a pulse to a gate thereof via the respective word line, wherein a duration of the pulse is greater than a duration of an access of the memory cell.

5. The memory device of claim 1 , wherein the memory element comprises a resistive switching memory element.

6. The memory device of claim 5 , wherein the resistive switching memory element comprises a phase change memory element.

7. A memory cell, comprising:

a memory element associated with a bit line; and

a trigger component configured to selectively electrically couple the memory element to the bit line for access thereto, wherein the trigger component comprises a thyristor having a gate coupled to a word line associated with the memory element.

8. The memory cell of claim 7 , wherein the thyristor is configured to couple the memory element to the bit line upon application of a pulse to the gate thereof via the word line.

9. The memory device of claim 7 , wherein the memory element comprises a resistive switching memory element.

10. The memory device of claim 9 , wherein the resistive switching memory element comprises a phase change memory element.

11. A memory device, comprising:

means for selectively electrically coupling a memory element to a bit line, wherein the coupling means is activated upon application of a pulse thereto provided on a word line, and wherein a duration of the pulse is less than a duration of the electrical coupling of the memory element to the bit line.

12. The memory device of claim 11 , wherein the coupling means comprises a thyristor having a gate terminal coupled to a word line, and wherein the pulse is applied to the gate terminal via the word line.

13. The memory device of claim 11 , wherein the memory element comprises a resistive switched memory element.

14. The memory device of claim 13 , wherein the resistive switched memory element comprises a phase change memory element.

15. A memory device, comprising:

an array of memory cells arranged in a plurality of rows and columns comprising word lines and bit lines, respectively, wherein each memory cell is selectively electrically coupled to a respective bit line via a trigger device configured to be activated by a pulse provided on a respective word line, the pulse having a duration that is less than an access duration associated therewith.

16. The memory device of claim 15 , wherein the each memory cell comprises a resistive switched memory component, and wherein the trigger device comprises a thyristor.

17. The memory device of claim 16 , wherein the thyristor comprises a vertical structure formed on a semiconductor substrate, and wherein the resistive switched memory component is formed over the vertical thyristor.

18. The memory device of claim 17 , wherein the respective bit line extends over and electrically couples to the resistive switched memory component, and wherein the respective word line surrounds and electrically couples to a gate terminal portion of the thyristor.

19. The memory device of claim 17 , wherein the respective bit line extends over and electrically couples to the resistive switched memory component, and wherein the respective word line laterally abuts and electrically couples to a gate terminal portion of the thyristor.

20. The memory device of claim 17 , wherein the thyristor comprises a lateral structure formed in or on a semiconductor substrate.

21. The memory device of claim 20 , wherein the respective bit line extends over and electrically couples to the respective switched memory component, and further comprising a conductive vertically extending contact electrically coupling the resistive switched memory component to the thyristor.

22. The memory device of claim 21 , wherein the respective word line runs under the respective bit line and over the thyristor, and makes electrical contact to a gate terminal thereof.

23. A method of accessing a memory cell selectively coupled to a bit line via a trigger component that is coupled to a word line, comprising:

raising the bit line to an access voltage; and

applying a pulse to the word line having a pulse duration that is less than a duration of an access of the memory cell.

24. The method of claim 23 , wherein the access comprises a read operation, and wherein applying the pulse activates the trigger component, thereby electrically coupling the memory cell to the bit line.

25. The method of claim 24 , wherein the trigger component comprises a thyristor, and wherein an activation time period thereof is greater than the pulse duration.

26. The method of claim 24 , further comprising lowering the bit line to a deactivation potential, thereby deactivating the trigger component.

27. The method of claim 23 , wherein the access comprises a write operation, and wherein applying the pulse activates the trigger component, thereby coupling the memory cell to the bit line.

28. The method of claim 27 , wherein the memory cell comprises a phase change memory element, and wherein the write operation comprises a set operation, wherein raising the bit line to the access voltage comprises raising the bit line to a set voltage level for a predetermined time period associated with the set operation.

29. The method of claim 27 , wherein the memory cell comprises a phase change memory element, and wherein the write operation comprises a reset operation, wherein raising the bit line to the access voltage comprises raising the bit line to a reset voltage level that is greater than a set voltage level for a predetermined time period associated with the reset operation that is shorter than a time period for a set operation.

30. A trigger memory, comprising a trigger element configured to selectively couple a memory component to a bit line for an activation time period based on an activation pulse supplied thereto via a word line, wherein a duration of the activation pulse is less than the activation time period.

31. The trigger memory of claim 30 , wherein the trigger element is further configured to be deactivated by supplying a deactivation signal on the bit line that is less than a predetermined threshold.