Resistive memory including refresh operation
View Patent ↗A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.
1. An integrated circuit comprising:
a plurality of resistive memory cells;
a counter having a first increment step at a first temperature and a second increment step greater than the first increment step at a second temperature greater than the first temperature; and
a circuit for refreshing the memory cells in response to the counter exceeding a preset value,
wherein the counter increments in response to each read access of the memory cells.
2. The integrated circuit of claim 1 , wherein the counter increments in response to each clock cycle of the integrated circuit.
3. The integrated circuit of claim 1 , wherein the plurality of resistive memory cells comprises an array of multi-bit resistive memory cells.
4. The integrated circuit of claim 1 , wherein the plurality of resistive memory cells comprises an array of phase change memory cells.
5. The integrated circuit of claim 1 , wherein the circuit is located on a same chip as the plurality of resistive memory cells.
6. A memory device comprising:
an array of resistive memory cells;
a counter configured to increment in response to each clock cycle of the memory device and in response to each read access of the memory device; and
a circuit for refreshing memory cells within the array in response to the counter exceeding a preset value,
wherein a first increment step of the counter for each clock cycle varies in response to a temperature of the memory device and a second increment step of the counter for each read access varies in response to the temperature.
7. The memory device of claim 6 , wherein the first increment step comprises a first step at a first temperature and a second step greater than the first step at a second temperature greater than the first temperature.
8. The memory device of claim 6 , wherein the second increment step comprises a first step at a first temperature and a second step greater than the first step at a second temperature greater than the first temperature.
9. The memory device of claim 6 , wherein the array of resistive memory cells comprises an array of multi-bit resistive memory cells.
10. The memory device of claim 6 , wherein the array of resistive memory cells comprises an array of phase change memory cells.
11. A memory device comprising:
an array of resistive memory cells;
a first counter configured to increment in response to each read access of the memory device;
a second counter configured to increment in response to each clock cycle of the memory device; and
a circuit configured to refresh memory cells within the array in response to the first counter exceeding a first preset value or in response to the second counter exceeding a second preset value,
wherein a first increment step of the first counter varies in response to a temperature of the memory device and a second increment step of the second counter varies in response to the temperature.
12. The memory device of claim 11 , wherein the first increment step comprises a first step at a first temperature and a second step greater than the first step at a second temperature greater than the first temperature.
13. The memory device of claim 11 , wherein the second increment step comprises a first step at a first temperature and a second step greater than the first step at a second temperature greater than the first temperature.
14. The memory device of claim 11 , wherein the array of resistive memory cells comprises an array of multi-bit resistive memory cells.
15. The memory device of claim 11 , wherein the array of resistive memory cells comprises an array of phase change memory cells.
16. A method for refreshing a memory, the method comprising:
incrementing a counter in response to each read access of the memory; and
refreshing resistive memory cells of the memory in response to the counter exceeding a preset value,
wherein incrementing the counter comprises incrementing the counter by a first step at a first temperature and incrementing the counter by a second step greater than the first step at a second temperature greater than the first temperature.
17. The method of claim 16 , wherein incrementing the counter comprises incrementing the counter in response to each clock cycle of the memory.
18. The method of claim 16 , wherein refreshing the resistive memory cells comprises refreshing multi-bit resistive memory cells.
19. The method of claim 16 , wherein refreshing the resistive memory cells comprises refreshing phase change memory cells.
20. A method for refreshing a memory, the method comprising:
incrementing a counter by a first increment step based on a temperature of the memory in response to each clock cycle of the memory;
incrementing the counter by a second increment step based on the temperature in response to each read access of the memory; and
refreshing resistive memory cells of the memory in response to the counter exceeding a preset value.
21. The method of claim 20 , wherein incrementing the counter in response to each clock cycle comprises incrementing the counter by a first step at a first temperature and incrementing the counter by a second step greater than the first step at a second temperature greater than the first temperature.
22. The method of claim 20 , wherein incrementing the counter in response to each read access comprises incrementing the counter by a first step at a first temperature and incrementing the counter by a second step greater than the first step at a second temperature greater than the first temperature.
23. The method of claim 20 , wherein refreshing the resistive memory cells comprises refreshing multi-bit resistive memory cells.
24. The method of claim 20 , wherein refreshing the resistive memory cells comprises refreshing phase change memory cells.
25. A method for refreshing a memory, the method comprising:
incrementing a first counter in response to each read access of the memory;
incrementing a second counter in response to each clock cycle of the memory; and
refreshing resistive memory cells of the memory in response to the first counter exceeding a first preset value or in response to the second counter exceeding a second preset value.
26. The method of claim 25 , wherein incrementing the first counter comprises incrementing the first counter by a first increment step based on a temperature of the memory, and wherein incrementing the second counter comprises incrementing the second counter by a second increment step based on the temperature.
27. The method of claim 26 , wherein incrementing the first counter by the first increment step comprises incrementing the first counter by a first step at a first temperature and by a second step greater than the first step at a second temperature greater than the first temperature.
28. The method of claim 26 , wherein incrementing the second counter by the second increment step comprises incrementing the second counter by a first step at a first temperature and by a second step greater than the first step at a second temperature greater than the first temperature.
29. The method of claim 25 , wherein refreshing the resistive memory cells comprises refreshing multi-bit resistive memory cells.
30. The method of claim 25 , wherein refreshing the resistive memory cells comprises refreshing phase change memory cells.