Reduced-delay clocked logic
View Patent ↗Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle.
1. A method of reducing delay in a clocked logic circuit, comprising:
partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle;
preventing the partially determined next state of the clocked logic circuit from affecting the current state of the clocked logic circuit during the first portion of the clock cycle;
completely determining the next state of the clocked logic circuit based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle; and
preventing the next state of the clocked logic circuit from affecting the partially determined next state of the clocked logic circuit during the second portion of the clock cycle.
2. The method of claim 1 , wherein partially determining the next state of the clocked logic circuit comprises partially determining a count value.
3. The method of claim 2 , wherein completely determining the next state of the clocked logic circuit comprises completely determining the count value based on a previously captured count value and the partially determined count value.
4. The method of claim 1 , wherein partially determining the next state of the clocked logic circuit comprises generating timing-critical state information.
5. The method of claim 1 , further comprising resetting the current state of the clocked logic circuit and the partially calculated next state of the clocked logic circuit responsive to a reset signal.
6. A clocked logic circuit, comprising:
first logic circuitry configured to partially determine a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle;
latch circuitry configured to prevent the partially determined next state of the clocked logic circuit from affecting the current state of the clocked logic circuit during the first portion of the clock cycle; and
second logic circuitry configured to completely determine the next state of the clocked logic circuit based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle,
wherein the latch circuitry is further configured to prevent the second logic circuitry from affecting operation of the first logic circuitry during the second portion of the clock cycle.
7. The clocked logic circuit of claim 6 , wherein the first logic circuitry is configured to partially determine a count value.
8. The clocked logic circuit of claim 7 , wherein the second logic circuitry is configured to completely determine the count value based on a previously captured count value and the partially determined count value.
9. The clocked logic circuit of claim 6 , wherein the first logic circuitry is configured to generate timing-critical state information.
10. The clocked logic circuit of claim 6 , wherein the latch circuitry is further configured to reset responsive to a reset signal.
11. An integrated circuit including the clocked logic circuit as claimed in claim 6 .
12. A method of reducing delay in a clocked logic circuit segmented into at least first and second stages, comprising:
during a first portion of a clock cycle:
partially determining a next state of the clocked logic circuit by the first stage based on a captured state of the clocked logic circuit; and
preventing the first stage from altering operation of the second stage; and
during a second portion of the clock cycle:
completely determining the next state of the clocked logic circuit by the second stage based on the captured state of the clocked logic circuit and the partially determined next state of the clocked logic circuit; and
preventing the second stage from altering operation of the first stage.
13. The method of claim 12 , wherein partially determining the next state of the clocked logic circuit comprises partially determining a count value.
14. The method of claim 13 , wherein completely determining the next state of the clocked logic circuit comprises completely determining the count value based on a previously captured count value and the partially determined count value.
15. The method of claim 12 , wherein partially determining the next state of the clocked logic circuit comprises generating timing-critical state information.
16. The method of claim 12 , further comprising resetting the first and second stages responsive to a reset signal.
17. A clocked logic circuit, comprising:
first and second logic stages; and
latch circuitry configured to:
capture a current state of the clocked logic circuit during a first portion of a clock cycle;
provide the captured state of the clocked logic circuit to the first logic stage, the first logic stage configured to partially determine a next state of the clocked logic circuit based on the captured state of the clocked logic circuit;
provide the captured state of the clocked logic circuit and the partially determined next state of the clocked logic circuit to the second logic stage during a second portion of the clock cycle, the second logic stage configured to completely determine the next state of the clocked logic circuit based on the captured state of the clocked logic circuit and the partially determined next state of the clocked logic circuit;
prevent the second logic stage from altering operation of the first logic stage during the second portion of the clock cycle; and
prevent the first logic stage from altering operation of the second logic stage during the first portion of the clock cycle.
18. The clocked logic circuit of claim 17 , wherein the first logic stage is configured to partially determine a count value based on the captured state of the clocked logic circuit.
19. The clocked logic circuit of claim 18 , wherein the second logic stage is configured to completely determine the count value based on a previously captured count value and the partially determined count value.
20. The clocked logic circuit of claim 17 , wherein the first logic stage is configured to generate timing-critical state information.
21. The clocked logic circuit of claim 17 , wherein the latch circuitry is further configured to reset responsive to a reset signal.
22. An integrated circuit including the clocked logic circuit as claimed in claim 17 .