Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
View Patent ↗The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprising a plurality of layers; and a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a control electrode comprising at least one layer different from said plurality of layers.
1. Integrated circuit comprising:
a plurality of first devices, each first device including a charge storage layer and a first control electrode comprising a first plurality of layers; and
a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a second control electrode comprising a second plurality of layers having at least one layer composed of a different material from said first plurality of layers, and wherein at least two of the first plurality of layers and at least two of the second plurality of layers are, respectively, the same layers.
2. The integrated circuit of claim 1 , wherein said plurality of first devices comprises TANOS gate stacks.
3. The integrated circuit of claim 1 , wherein said plurality of first devices comprises SONOS gate stacks.
4. The integrated circuit of claim 1 , wherein said plurality of second devices does not include a charge storage layer.
5. The integrated circuit of claim 1 , wherein the second control electrode of said plurality of second devices includes a polysilicon layer.
6. The integrated circuit of claim 1 , wherein the first control electrode of said plurality of first devices and the second control electrode of said plurality of second devices include at least one of a tungsten and a tungsten nitride layer.
7. The integrated circuit of claim 1 , wherein said first devices comprise first gate stacks and said second devices comprise second gate stacks.
8. The integrated circuit of claim 1 , further comprising a plurality of third devices, each third device including a third control electrode comprising a third plurality of layers, said layers not including a charge storage layer.
9. Memory device including the integrated circuit of claim 1 .
10. The memory device of claim 9 , wherein said first devices comprise non-volatile memory cells and said second devices comprise select gates and wherein said first and second devices are located in a memory array region.
11. The memory device of claim 9 , wherein said plurality of first devices comprises TANOS gate stacks.
12. The memory device of claim 9 , wherein said plurality of first devices comprises SONOS gate stacks.
13. The memory device of claim 9 , comprising a plurality of third devices, each third device including a third control electrode comprising a third plurality of layers, said layers not including a charge storage layer, wherein said third devices comprise peripheral device gate stacks.
14. Integrated circuit comprising:
a plurality of first devices, each first device including a charge storage layer and a first control electrode comprising a first plurality of layers; and
a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a second control electrode comprising a second plurality of layers;
wherein said first plurality of layers having at least one layer composed of a different material from said second plurality of layers, and wherein at least two of the first plurality of layers and at least two of the second plurality of layers are, respectively, the same layers.