Method of producing an integrated circuit having a capacitor with a supporting layer

1. A method of producing an integrated circuit having a capacitor element with a first electrode, a dielectric layer and a second electrode comprising:

depositing a sacrificial layer on a substrate;

forming recesses in the sacrificial layer;

depositing the first electrodes in the recesses;

depositing a supporting layer on a planar surface of the sacrificial layer and the first electrodes, the supporting layer being connected with the first electrodes stabilizing the first electrodes;

forming openings in the supporting layer beside the first electrodes such that the supporting layer remains over the first electrodes;

removing at least partially the sacrificial layer through the openings;

removing the supporting layer with a dry etching process; and

forming the dielectric layer and the second electrode completing the capacitor element.

2. The method of claim 1 , wherein the first electrodes are formed in a cup shape.

3. The method of claim 1 , wherein the supporting layer comprises carbon.

4. The method of claim 1 , wherein the supporting layer is deposited over the first electrodes covering the first electrodes.

5. The method of claim 1 , comprising:

forming the first electrodes in cup shapes;

depositing the supporting layer on upper end faces of the first electrodes covering the first electrodes; and

removing at least partially the sacrificial layer by a wet etching process.

6. The method of claim 1 , wherein the supporting layer is deposited on the sacrificial layer adjacent to upper end faces of the first electrodes connecting at least two first electrodes of two capacitor elements.

7. The method of claim 1 , further comprising:

filling the recesses with a sacrificial material; and

removing the sacrificial material before depositing the dielectric layers on the first electrodes.

8. The method of claim 1 , wherein the sacrificial layer is removed by a wet etching process.

9. The method of claim 1 , wherein the supporting layer is removed at a temperature lower than 250° C.

10. The method of claim 9 , wherein the supporting layer is removed with an oxygen-free gas.

11. The method of claim 1 , further comprising depositing a further layer on the supporting layer, using the further layer as a hard mask for structuring the supporting layer.

12. A method of forming a semiconductor memory having capacitor elements with first electrodes, dielectric layers and second electrodes, the method comprising:

depositing a sacrificial layer on a substrate;

forming recesses in the sacrificial layer;

depositing the first electrodes in the recesses;

depositing a supporting layer on a planar surface of the sacrificial layer and the first electrodes, forming at least one opening in the supporting layer beside the first electrodes such that the supporting layer remains over the first electrodes, the supporting layer being connected with the first electrodes stabilizing the first electrodes;

removing at least partially the sacrificial layer via the opening;

removing the supporting layer; and

forming the dielectric layer and the second electrode completing the capacitor element of the semiconductor memory.

13. The method of claim 12 , wherein the first electrodes are formed in a cup shape.

14. The method of claim 12 , wherein the supporting layer comprises carbon.

15. The method of claim 12 , wherein the supporting layer is deposited over the first electrodes covering the first electrodes.

16. The method of claim 12 , wherein the first electrodes are formed in cup shapes, wherein the supporting layer is deposited on upper end faces of the first electrodes covering the first electrodes, wherein the sacrificial layer is removed by a wet etching process, and wherein the supporting layer is removed by a dry etching process.

17. The method of claim 12 , further comprising after depositing the first electrodes:

filling the recesses with a sacrificial material;

removing sacrificial material from the first electrodes before forming the dielectric layer on the first electrodes,

wherein the supporting layer is deposited on the sacrificial layer before forming the recesses in the supporting layer and the sacrificial layer.

18. A method of forming capacitor elements with first electrodes, dielectric layers, and second electrodes, the method comprising:

providing a substrate comprising first electrodes formed in recesses in a sacrificial layer, wherein a supporting layer is arranged above a planar surface of the sacrificial layer;

forming an opening in the supporting layer beside the first electrodes such that the supporting layer remains above the first electrodes;

removing at least partially the sacrificial layer through the opening, wherein the first electrodes are stabilized by the supporting layer;

removing the supporting layer; and

forming the dielectric layer and the second electrode completing the capacitor element.

19. The method of claim 18 , wherein the first electrodes are formed in a cup shape.

20. The method of claim 18 , wherein the supporting layer comprises carbon.

21. The method of claim 18 , wherein the supporting layer is formed after the first electrodes and is in contact with the first electrodes, and wherein the supporting layer connects at least two first electrodes.

22. The method of claim 18 , wherein providing the substrate comprises:

depositing the sacrificial layer;

forming recesses in the sacrificial layer

forming the first electrodes in the recesses; and

covering the first electrodes with a further sacrificial material.

23. The method of claim 18 , wherein providing the substrate comprises:

depositing the sacrificial layer;

depositing the supporting layer on the sacrificial layer;

forming the recesses in the supporting layer and the sacrificial layer; and

then depositing the first electrodes in the recesses in contact with the sacrificial layer and the supporting layer.

24. The method of claim 18 , wherein the supporting layer comprises carbon, and wherein removing the supporting layer comprises a carbon ashing process.

25. A method of producing an integrated circuit having a memory with capacitor elements including a first electrode, a dielectric layer and a second electrode comprising:

providing a substrate comprising first electrodes formed in recesses in a sacrificial layer, wherein a supporting layer is arranged above a planar surface of the sacrificial layer;

forming an opening in the supporting layer beside the first electrodes such that the supporting layer remains above the first electrodes;

removing at least partially the sacrificial layer through the opening, the supporting layer supporting the first electrodes during the removal of the sacrificial layer;

removing the supporting layer; and

depositing the dielectric layers and the second electrodes on the first electrodes completing the capacitor elements for memory.