IP Library Granted Patent US 7,587,571
Granted Patent B2
US 7,587,571 · App. 11/564,764 · Granted Sep 8, 2009

Evaluation unit in an integrated circuit

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Quick Facts
Patent No.
US 7,587,571
App. No.
11/564,764
Granted
Sep 8, 2009
Kind
B2
Abstract

An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to the first terminal and to the evaluation unit, the switching unit admitting signal exchange via the first terminal if the evaluation unit does not determine the predetermined signal level, the switching unit cutting off signal exchange via the first terminal if the evaluation unit determines the predetermined signal level.

Claims (22)

1. A memory module, comprising:

a memory controller having a first terminal for exchanging data; and

a memory device, the memory having:

a second terminal for exchanging data;

an evaluation unit coupled to the second terminal, the evaluation unit evaluating a signal level applied to the second terminal to determine whether the applied signal level corresponds to a predetermined signal level; and

a switching unit coupled to the second terminal and to the evaluation unit, the switching unit being configured to admit data exchange via the second terminal to the first terminal of the memory controller when the evaluation unit determines that the applied signal level does not correspond to the predetermined signal level, the switching unit being further configured to cut off data exchange via the second terminal if the evaluation unit determines that the applied signal level corresponds to the predetermined signal level.

2. The memory module as claimed in claim 1 , wherein the second terminal of the memory device is coupled to a signal source via a fixed connection when the predetermined signal level is applied to the second terminal.

3. The memory module as claimed in claim 2 , wherein the second terminal of the memory device is coupled to a voltage source.

4. The memory module as claimed in claim 1 ,

wherein the memory controller comprises a transmitting unit coupled to a third terminal;

wherein the memory device comprises a fourth terminal coupled to the third terminal of the memory controller and to the switching unit of the memory device; and

wherein the switching unit of the memory device is configured to sample the signal level determination of the evaluation unit in conjunction of a data signal applied by the transmitting unit of the memory controller via the third terminal and the fourth terminal.

5. The memory module as claimed in claim 4 ,

wherein the switching unit of the memory device is a flip-flop.

6. The memory module as claimed in claim 1 ,

wherein the memory controller further comprises a termination resistor, a termination switch, a termination voltage terminal, a receiving unit and a transmitting unit;

wherein the first terminal of the memory controller is coupled to the receiving unit and to the termination voltage terminal via the termination switch and the termination resistor; and

wherein the first terminal of the memory controller is coupled to the second terminal of the memory device via at least a signal line when the predetermined signal level is not applied to the second terminal of the memory device.

7. The memory module as claimed in claim 1 ,

wherein the second terminal of the memory device comprises at least two data ports;

wherein the evaluation unit of the memory device is configured to evaluate the signal level applied to at least one data port of the at least two data ports of the second terminal to determine whether the applied signal level corresponds to the predetermined signal level; and

wherein the switching unit of the memory device is configured to admit data exchange via the at least two data ports of second terminal when the evaluation unit of the memory device determines that the applied signal level does not correspond to the predetermined signal level and cut off data exchange via the at least two data ports of the first terminal when the evaluation unit of the memory device determines that the applied signal level corresponds to the predetermined signal level.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2007
From: HEIN, THOMAS; NYGREN, AARON JOHN; KHO, REX
To: QIMONDA AG
Reel/Frame 019088/0563 →