IP Library Granted Patent US 7,564,114
Granted Patent B2
US 7,564,114 · App. 11/644,090 · Granted Jul 21, 2009

Semiconductor devices and methods of manufacture thereof

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Quick Facts
Patent No.
US 7,564,114
App. No.
11/644,090
Granted
Jul 21, 2009
Kind
B2
Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Claims (41)

1. A method of forming an insulating material, the method comprising:

forming an interface layer;

removing a portion of the interface layer;

annealing the interface layer;

exposing the annealed interface layer to nitrogen; and

forming a dielectric material over the interface layer.

2. The method according to claim 1 , wherein exposing the interface layer to nitrogen comprises: exposing the interface layer to a nitrogen-containing gas or liquid, exposing the interface layer to a plasma nitridation process, exposing the interface layer to a thermal nitridation process, or exposing the interface layer to an implantation process.

3. The method according to claim 1 , wherein forming the interface layer comprises forming the interface layer by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE).

4. The method according to claim 1 , wherein forming the interface layer comprises forming an interface layer comprising SiO 2 , LaAlO 3 , La(RE)O 3 , or Sc(RE)O 3 , wherein RE comprises a rare earth metal.

5. The method according to claim 1 , wherein forming the interface layer comprises forming an interface layer including a rare earth metal comprising Scandium (Sc), Yttrium (Y), Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), and/or Lutetium (Lu).

6. The method according to claim 1 , wherein annealing the interface layer comprises subjecting the interface layer to a high temperature rapid thermal anneal at a temperature of between about 1,000 and 1,250 degrees C.

7. The method according to claim 1 , wherein forming the dielectric material comprises forming HfO x , ZrO x , LaO x , HfSiO, ZrSiO, LaSiO, HfSi x O y N z , ZrSi x O y N z , LaSi x O y N z , laminates thereof, multiple layers thereof, one or more rare earth element, an oxide of at least one rare earth element, or at least one rare earth element and at least one transition metal.

8. A method of fabricating a semiconductor device, the method comprising:

providing a workpiece;

forming an interface layer directly onto a top surface of the workpiece, said interface layer having a thickness no greater than 5 nm;

removing a top portion of the interface layer to reduce the remaining thickness of said interface layer to 1 nm or less;

annealing the workpiece at a temperature of greater than about 1,000 degrees C. subsequent to removing a top portion; and

forming a dielectric material over the interface layer.

9. The method according to claim 8 , wherein removing a portion of the interface layer comprises removing about one half or greater of the interface layer.

10. The method according to claim 8 , wherein annealing the workpiece comprises a flash anneal process, a spike anneal process, or a rapid thermal anneal (RTA) process.

11. The method according to claim 8 , wherein forming the interface layer comprises a steam based thermal oxide deposition process.

12. The method according to claim 8 , wherein forming the interface layer comprises forming a ternary oxide.

13. The method of claim 9 further comprising exposing the interface layer to nitrogen subsequent to said annealing its interface.

14. A method of forming an insulating material, the method comprising: forming an interface layer directly onto the surface of a workpiece, said interface layer having a thickness no greater than 5 nm;

removing a top portion of the interface layer to reduce the thickness of said interface layer to 1 nm or less;

annealing the interface layer subsequent to removing a top portion of the interface layer; and

forming a dielectric material over the interface layer.

15. A method of fabricating a semiconductor device, the method comprising:

providing a workpiece;

cleaning the workpiece;

forming an interface layer over the workpiece;

removing a portion of the interface layer so that the thickness of the interface layer comprises about 1 nm or less;

annealing the workpiece to densify the interface layer;

forming a dielectric material over the interface layer, wherein the interface layer and the dielectric material comprise an insulating material; and

forming a conductive material over the dielectric material.

16. The method according to claim 15 , wherein forming the dielectric material comprises forming a material having a thickness of about 15 nm or less.

17. The method according to claim 15 , further comprising nitriding the interface layer after annealing the workpiece, forming a nitrided surface on the interface layer.

18. The method according to claim 17 , wherein nitriding the interface layer comprises a nitridation process in a N 2 or NH 3 ambient at a temperature of between about 550 to 800° C. for about 10 to 60 seconds, or a uniform surface nitridation process in a plasma nitridation chamber.

19. The method according to claim 15 , wherein forming the dielectric material comprises forming a dielectric material having a dielectric constant (k) greater than about 3.9.

20. The method according to claim 15 , wherein forming the interface layer and forming the dielectric material comprise forming an insulating material comprising a gate dielectric of a transistor or a capacitor dielectric of a capacitor.

21. The method according to claim 15 , wherein forming the conductive material comprises forming TiN, TaN, Ru, RuO 2 , TiSiN, TaSiN, HfSiN, TiHfN, TiCN, TaCN, TiXN, AlN, RE 1 RE 2 N, polysilicon, and/or multiple layers or combinations thereof, wherein X comprises a rare earth element, wherein RE 1 RE 2 N comprises a nitride of a first rare earth element RE 1 and a second rare earth element RE 2 , and wherein the second rare earth element comprises a different rare earth element than the first rare earth element.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2020
From: POLARIS INNOVATIONS LIMITED
To: CHANGXIN MEMORY TECHNOLOGIES, INC
Reel/Frame 051917/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: QIMONDA NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 026138/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2007
From: GOVINDARAJAN, SHRINIVAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018896/0313 →