Method and apparatus for increasing clock frequency and data rate for semiconductor devices

1. An apparatus for enhancing a data rate of a data signal including a data pattern for storage in a memory device comprising:

a data circuit to receive at least one data shift signal and a data signal including a data pattern for storage in a memory device and a first data rate associated with a first clock signal frequency, and to produce a resulting data signal including a second data rate associated with a second clock signal frequency, wherein each said data shift signal includes a phase shifted version of said data signal and said second clock signal frequency and said second data rate are respectively greater than said first clock signal frequency and said first data rate, and wherein said data circuit includes a data logic circuit to combine said data and data shift signals to produce said resulting data signal with said data pattern for storage in said memory device.

2. The apparatus of claim 1 further comprising:

a clock circuit to receive a clock signal with said first clock signal frequency and at least one differential signal phase shifted relative to said clock signal and to produce a resulting clock signal with said second clock signal frequency by combining said clock and differential signals to enable storage of said data pattern of said resulting data signal by said memory device.

3. The apparatus of claim 1 , wherein said data logic circuit comprises:

a logic circuit to perform an exclusive-OR operation of said data signal and said at least one data shift signal to produce said resulting data signal.

4. The apparatus of claim 2 , wherein said clock circuit comprises:

a logic circuit to perform an exclusive-OR operation of said clock signal and said at least one differential signal to produce said resulting clock signal.

5. The apparatus of claim 2 , wherein:

said at least one data shift signal comprises a signal phase shifted by ninety degrees relative to said data signal to produce said resulting data signal with said second data rate twice that of said first data rate; and

said at least one differential signal comprises a signal phase shifted by ninety degrees relative to said clock signal to produce said resulting clock signal with said second clock signal frequency twice that of said first clock signal frequency.

6. The apparatus of claim 2 , wherein said apparatus comprises a memory device comprising a plurality of said data circuits, and at least one data line, wherein said data circuits and said clock circuit are disposed on said memory device with each data circuit associated with a corresponding data line of said memory device, and wherein said clock signal, said at least one differential signal, said data signal and said at least one data shift signal are received from an external device to produce said resulting clock and data signals.

7. The apparatus of claim 6 , wherein at least one of said data signal and said data shift signal is adjusted to control set-up and hold times of said memory device.

8. An apparatus for enhancing a data rate of a data signal including a data pattern for storage in a memory device comprising:

data signal means for receiving at least one data shift signal and a data signal including a data pattern for storage in a memory device and a first data rate associated with a first clock signal frequency, wherein each said data shift signal includes a phase shifted version of said data signal; and

data means for logically combining said data signal and said at least one data shift signal to produce a resulting data signal including a second data rate associated with a second clock signal frequency and said data pattern for storage in said memory device, wherein said second clock signal frequency and said second data rate are respectively greater said first clock signal frequency and said first data rate.

9. The apparatus of claim 8 further comprising:

clock signal means for receiving a clock signal with said first clock signal frequency and at least one differential signal phase shifted relative to said clock signal; and

clock means for producing a resulting clock signal with said second clock signal frequency by combining said clock and differential signals to enable storage of said data pattern of said resulting data signal by said memory device.

10. The apparatus of claim 8 , wherein said data means comprises:

logic means for performing an exclusive-OR operation of said data signal and said at least one data shift signal to produce said resulting data signal.

11. The apparatus of claim 9 , wherein said clock means comprises:

logic means for performing an exclusive-OR operation of said clock signal and said at least one differential signal to produce said resulting clock signal.

12. The apparatus of claim 9 , wherein:

said at least one data shift signal comprises a signal phase shifted by ninety degrees relative to said data signal to produce said resulting data signal with said second data rate twice that of said first data rate; and

said at least one differential signal comprises a signal phase shifted by ninety degrees relative to said clock signal to produce said resulting clock signal with said second clock signal frequency twice that of said first clock signal frequency.

13. The apparatus of claim 9 , wherein said apparatus comprises a memory device comprising a plurality of said data signal means and said data means, and at least one data line, wherein said plurality of data signal means, said plurality of data means, said clock signal means and said clock means are disposed on said memory device with each data signal means and data means associated with a corresponding data line of said memory device, and wherein said clock signal, said at least one differential signal, said data signal and said at least one data shift signal are received from an external device to produce said resulting clock and data signals.

14. A memory device for enhancing a data rate of a data signal including a data pattern for storage in said memory device comprising:

a plurality of clock lines to receive a clock signal including a first clock signal frequency and at least one differential clock signal phase shifted relative to said clock signal;

at least one data line to receive a data signal including a first data rate associated with said first clock signal frequency and a data pattern for storage in said memory device;

at least one data shift line to receive at least one data shift signal each including a phase shifted version of said data signal; and

at least one data circuit, associated with said at least one data line, to receive said data signal and said at least one data shift signal and to combine said data and data shift signals to produce a resulting data signal including a second data rate associated with a second clock signal frequency and said data pattern for storage in said memory device, wherein said second clock signal frequency and said second data rate are respectively greater than said first clock signal frequency and said first data rate.

15. The memory device of claim 14 further comprising:

a clock circuit to receive said clock signal and said at least one differential signal and produce a resulting clock signal with said second clock signal frequency by combining said clock and differential signals to enable storage of said data pattern of said resulting data signal by said memory device.

16. The memory device of claim 14 , wherein said data circuit comprises:

a logic circuit to perform an exclusive-OR operation of said received data signal and said at least one data shift signal to produce said resulting data signal.

17. The memory device of claim 15 , wherein said clock circuit comprises:

a logic circuit to perform an exclusive-OR operation of said clock signal and said at least one differential signal to produce said resulting clock signal.

18. The memory device of claim 15 , wherein said at least one data shift signal comprises a signal phase shifted by ninety degrees relative to said data signal to produce said resulting data signal with said second data rate twice that of said first data rate.

19. The memory device of claim 14 , wherein said clock signal, said at least one differential signal, said data signal and said at least one data shift signal are received from an external device to produce said resulting clock and data signals.

20. The memory device of claim 14 , wherein at least one of said data signal and said data shift signal is adjusted to control set-up and hold times of said memory device.

21. A method of enhancing a data rate of a data signal including a data pattern for storage in a memory device comprising:

(a) receiving at least one data shift signal and a data signal including a data pattern for storage in a memory device and a first data rate associated with a first clock signal frequency, wherein each said data shift signal includes a phase shifted version of said data signal; and

(b) producing a resulting data signal including a second data rate associated with a second clock signal frequency and said data pattern for storage in said memory device by combining said data and data shift signals, wherein said second clock signal frequency and said second data rate are respectively greater than said first clock signal frequency and said first data rate.

22. The method of claim 21 further comprising:

(c) receiving a clock signal and at least one differential signal phase shifted relative to said clock signal; and

(d) producing a resulting clock signal with said second clock signal frequency by combining said clock and differential signals to enable storage of said data pattern of said resulting data signal by said memory device.

23. The method of claim 21 , wherein step (b) further comprises:

(b.1) performing an exclusive-OR operation of said data signal and said at least one data shift signal to produce said resulting data signal.

24. The method of claim 22 , wherein step (d) further comprises:

(d.1) performing an exclusive-OR operation of said clock signal and said at least one differential signal to produce said resulting clock signal.

25. The method of claim 22 , wherein step (a) further comprises:

(a.1) receiving said at least one data shift signal comprising a signal phase shifted by ninety degrees relative to said data signal;

step (b) further comprises:

(b.1) producing said resulting data signal with said second data rate twice that of said first data rate;

step (c) further comprises:

(c.1) receiving said at least one differential signal comprising a signal phase shifted by ninety degrees relative to said clock signal; and

step (d) further comprises:

(d.1) producing said resulting clock signal with said second clock signal frequency twice that of said first clock signal frequency.

26. The method of claim 22 , wherein said device comprises a memory device, and step (a) further includes:

(a.1) receiving said data signal and said at least one data shift signal from an external device;

step (b) further includes:

(b.1) producing said resulting data signal;

step (c) further includes:

(c.1) receiving said clock signal and said at least one differential signal from said external device; and

step (d) further includes:

(d.1) producing said resulting clock signal.

27. The method of claim 26 , wherein step (a) further includes:

(a.2) adjusting at least one of said data signal and said data shift signal to control set-up and hold times of said memory device.