Integrated circuit memory device responsive to word line/bit line short-circuit
View Patent ↗An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.
1. An integrated circuit device, comprising:
a word line;
a bit line;
a first switching device connected between the word line and a first voltage source supplying a negative voltage, the first switching device having a gate terminal;
a driver circuit outputting a control signal to the gate terminal of the first switching device in response to a short-circuit between the word line and the bit line.
2. The integrated circuit device of claim 1 , wherein the driver circuit includes a first input configured to indicate the short-circuit between the word line and the bit line.
3. The integrated circuit device of claim 2 , wherein the driver circuit includes a second input, wherein the control signal is output further in response to the second input.
4. The integrated circuit device of claim 3 , wherein the driver circuit includes a delay circuit configured to delay the control signal output for a predetermined time period.
5. The integrated circuit device of claim 1 , further comprising a second switching device connected between the word line and the first voltage source.
6. The integrated circuit device of claim 5 , wherein the first and second switching devices are connected in parallel.
7. A memory device, comprising:
an array of memory cells;
a plurality of word lines;
a plurality of bit lines;
a first switching device connected between a selected one of the word lines and a first voltage source supplying a negative voltage, the first switching device having a gate terminal;
a driver circuit outputting a control signal to the gate terminal of the first switching device in response to a short-circuit between the selected word line and one of the plurality of bit lines.
8. The memory device of claim 7 , wherein the driver circuit includes a first input configured to indicate the short-circuit.
9. The memory device of claim 8 , wherein the driver circuit includes a second input identifying the selected word line, wherein the control signal is output further in response to the second input.
10. The memory device of claim 9 , wherein the driver circuit includes a delay circuit configured to delay the control signal output for a predetermined time period.
11. The memory device of claim 7 , further comprising a second switching device connected between the word line and the first voltage source.
12. The memory device of claim 11 , wherein the first and second switching devices are connected in parallel.
13. A memory device, comprising:
an array of memory cells;
a plurality of word lines;
a plurality of bit lines;
means for limiting current flow resulting from a short-circuit between the word line and bit line.
14. A method for operating a memory device, comprising:
connecting a pair of bit lines to a first voltage source to precharge the pair of bit lines to a preselected voltage level;
activating a first switch to connect a word line to a second voltage source that supplies a negative voltage;
deactivating the first switch in response to a short-circuit between the word line and one of the bit lines.
15. The method of claim 14 , further comprising activating a second switch connected in parallel with the first switch to connect the word line to the second voltage source.
16. The method of claim 15 , wherein the second switch remains activated when the first switch is deactivated in response to the short-circuit.
17. The method of claim 14 , wherein the first switch includes a gate terminal, the method further comprising outputting a control signal to the gate terminal in response to a first input signal indicating the short-circuit.
18. The method of claim 17 , wherein the control signal is further responsive to a second input signal identifying the word line.
19. The method of claim 18 , further comprising delaying the first input signal by a predetermined time period.
20. The method of claim 14 , wherein a row redundancy scheme is used to determine the presence of a short-circuit.
21. An integrated circuit device, comprising:
a word line;
a bit line;
a first switching device connected between the word line and a first voltage source, the first switching device having a gate terminal;
a driver circuit outputting a control signal to the gate terminal of the first switching device in response to a short-circuit between the word line and the bit line, wherein the driver circuit includes:
a first input configured to indicate the short-circuit between the word line and the bit line;
a second input, wherein the control signal is output further in response to the second input; and
a delay circuit configured to delay the control signal output for a predetermined time period.
22. The integrated circuit device of claim 21 , wherein the first voltage source supplies a negative voltage.