Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor
View Patent ↗An integrated circuit includes a field effect transistor formed in an active area segment of a semiconductor substrate. The transistor comprises: a first source/drain contact region including a first vertical extension and a second source/drain contact region including a second vertical extension and a channel region formed around a recessed channel transistor groove, the groove being formed in the active area segment and extending to a groove depth larger than a lower first contact region depth, wherein the second vertical extension of the second source/drain contact region is arranged above the first extension of the first source/drain contact region, and wherein the recessed channel transistor groove is filled with a conductive gate material at a groove depth lower than the first contact region depth.
1. An integrated circuit including a field effect transistor formed in an active area segment of a semiconductor substrate, the transistor comprising:
a first source/drain contact region including a first vertical extension and a second source/drain contact region including a second vertical extension; and
a channel region formed around a recessed channel transistor groove, the groove being formed in the active area segment and extending to a groove depth larger than a lower first contact region depth,
wherein the second vertical extension of the second source/drain contact region is arranged above the first extension of the first source/drain contact region, and
wherein the recessed channel transistor groove is filled with a conductive gate material at a groove depth lower than the first contact region depth.
2. The integrated circuit according to claim 1 , wherein a first contact element adjoins the first source/drain contact region and a second contact element adjoins the second source/drain contact region.
3. The integrated circuit according to claim 2 , wherein at least one of the first and second contact elements comprise a metal line.
4. The integrated circuit according to claim 1 , wherein the second source/drain contact region is located on a side of the active area segment opposite to the first source/drain contact region, and said recessed channel transistor groove is arranged between the first and the second source/drain contact region.
5. The integrated circuit according to claim 1 , wherein the integrated circuit is formed on a semiconductor material, and the first source/drain contact region is located below the surface of the semiconductor material.
6. The integrated circuit according to claim 5 , wherein the first source/drain contact region is located in an isolation trench.
7. The integrated circuit according to claim 5 , wherein the second source/drain contact region is located below the surface of the semiconductor material.
8. The integrated circuit according to claim 1 , wherein a gate dielectric layer is disposed between the gate material and the channel region.
9. The integrated circuit according to claim 1 , wherein the integrated circuit is a memory device.
10. The integrated circuit according to claim 9 , wherein the integrated circuit is a DRAM.
11. The integrated circuit according to claim 10 , wherein the transistor is a selection transistor of a memory cell.