An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA.
1. An integrated circuit comprising:
a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5 V to approximately 3 V, and at a current in a range of approximately 1 μA to approximately 150 μA for write or erase operation of a bit, wherein the carbon storage layer comprises a narrow constriction, with a cross-sectional area of the constriction being smaller than a cross-sectional area of the top contact or the bottom contact.
2. The integrated circuit of claim 1 , wherein the memory cell is a non-volatile memory cell.
3. The integrated circuit of claim 1 , wherein the cross-sectional area of the constriction of the carbon storage layer is smaller than the cross-sectional area of the top contact or the bottom contact by a factor of approximately 10 to approximately 400.
4. The integrated circuit of claim 1 , wherein the cross-sectional area of the constriction of the carbon storage layer is smaller than the cross-sectional area of the top contact or of the bottom contact by a factor of approximately 350.
5. The integrated circuit of claim 1 , wherein the carbon storage layer comprises a carbon cladding disposed on an inner surface of a via.
6. The integrated circuit of claim 5 , wherein the carbon storage layer has a thickness in a range of approximately 1 nm to approximately 2 nm.
7. The integrated circuit of claim 5 , wherein the via has a diameter of approximately 10 nm or less.
8. The integrated circuit of claim 7 , wherein the via has a diameter in a range of approximately 1 nm to approximately 10 nm.
9. The integrated circuit of claim 5 , wherein the via has a depth of approximately 30 nm or less.
10. The integrated circuit of claim 1 , wherein the memory cell operates at a current of approximately 100 μA or less.
11. The integrated circuit of claim 1 , wherein the carbon storage layer stores information by a phase change in the carbon storage layer.
12. The integrated circuit of claim 1 , wherein the carbon storage layer stores information by formation of a conductive path in the carbon storage layer.
13. An integrated circuit comprising:
a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5 V to approximately 3 V, and at a current in a range of approximately 1 μA to approximately 150 μA for write or erase operation of a bit, wherein the carbon storage layer comprises a narrow constriction, with a cross-sectional area of the constriction being smaller than a cross-sectional area of the top contact or the bottom contact, and wherein the narrow constriction of the carbon storage layer encourages the formation of only a single conductive path within the carbon storage layer.
14. An integrated circuit comprising:
a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5 V to approximately 3 V, and at a current in a range of approximately 1 μA to approximately 150 μA for write or erase operation of a bit, wherein the carbon storage layer has a thickness in a range of approximately 1 nm to approximately 5 nm.
15. An integrated circuit comprising:
a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5 V to approximately 3 V, and at a current in a range of approximately 1 μA to approximately 150 μA for write or erase operation of a bit, wherein the carbon storage layer has a diameter below approximately 10 nm.
16. The integrated circuit of claim 15 , wherein the diameter of the carbon storage layer is in a range of approximately 1 nm to approximately 4 nm.
17. An integrated circuit comprising:
a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5 V to approximately 3 V, and at a current in a range of approximately 1 μA to approximately 150 μA for write or erase operation of a bit, wherein the memory cell uses a current pulse having a falling flank of approximately 10 ns or shorter for switching from a high conductivity state into a low conductivity state.
18. An integrated circuit comprising:
a memory cell comprising a select transistor and a carbon memory element electrically coupled to the select transistor, the carbon memory element comprising a top contact, a bottom contact, and a narrow carbon structure, the narrow carbon structure having a cross-sectional area that is smaller by a factor of approximately 10 to approximately 400 than a cross-sectional area of the top contact on a cross-sectional area of the bottom contact.
19. The integrated circuit of claim 18 , wherein the narrow carbon structure has a diameter below approximately 10 nm.
20. The integrated circuit of claim 19 , wherein the diameter of the narrow carbon structure is in a range of approximately 1 nm to approximately 4 nm.
21. The integrated circuit of claim 18 , wherein the carbon memory element comprises a non-volatile memory element.
22. The integrated circuit of claim 18 , wherein the memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA.
23. The integrated circuit of claim 22 , wherein the memory cell operates at a current of approximately 100 μA or less.
24. The integrated circuit of claim 18 , wherein the memory cell uses a current pulse having a falling flank of approximately 10 ns or shorter for switching from a high conductivity state into a low conductivity state.
25. The integrated circuit of claim 18 , wherein the narrow carbon structure stores information by a phase change.
26. The integrated circuit of claim 18 , wherein the narrow carbon structure stores information by formation of a conductive path.
27. A memory module comprising:
a multiplicity of integrated circuits, wherein said integrated circuits comprise a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA, wherein the carbon storage layer has a thickness in a range of approximately 1 nm to approximately 5 nm.
28. The memory module of claim 27 , wherein the memory cell is a non-volatile memory cell.
29. The memory module of claim 27 , wherein the carbon storage layer comprises a narrow constriction, the constriction having a cross-sectional area that is smaller than a cross-sectional area of the top contact or a cross-sectional area of the bottom contact.
30. The memory module of claim 27 , wherein the carbon storage layer has a diameter below approximately 10 nm.
31. The memory module of claim 27 , wherein the carbon storage layer comprises a carbon cladding disposed on an inner surface of a via.
32. The memory module of claim 31 , wherein the carbon cladding has a thickness in a range of approximately 1 nm to approximately 2 nm.
33. The memory module of claim 31 , wherein the via has a diameter of approximately 10 nm or less.
34. The memory module of claim 27 , wherein the memory cell uses a current pulse having a falling flank of approximately 10 ns or shorter for switching from a high conductivity state into a low conductivity state.
35. The memory module of claim 27 , wherein the carbon storage layer stores information by a phase change in the carbon storage layer.
36. The memory module of claim 27 , wherein the carbon storage layer stores information by formation of a conductive path in the carbon storage layer.
37. The memory module of claim 27 , wherein the memory module is stackable.
38. A computing system comprising:
an input apparatus;
an output apparatus;
a processing apparatus; and
a memory, said memory comprising a memory cell comprising a resistive memory element that comprises a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact, the memory cell operating at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA, wherein the carbon storage layer has a thickness in a range of approximately 1 nm to approximately 5 nm.
39. The computing system of claim 38 , wherein the memory cell is a non-volatile memory cell.
40. The computing system of claim 38 , wherein the carbon storage layer comprises a narrow constriction, the constriction having a cross-sectional area that is smaller than a cross-sectional area of the top contact or a cross-sectional area of the bottom contact.
41. The computing system of claim 38 , wherein the carbon storage layer has a diameter below approximately 10 nm.
42. The computing system of claim 38 , wherein the carbon storage layer comprises a carbon cladding disposed on an inner surface of a via.
43. The computing system of claim 42 , wherein the carbon cladding has a thickness in a range of approximately 1 nm to approximately 2 nm.
44. The computing system of claim 42 , wherein the via has a diameter of approximately 10 nm or less.
45. The computing system of claim 38 , wherein the memory cell uses a current pulse having a falling flank of approximately 10 ns or shorter for switching from a high conductivity state into a low conductivity state.
46. The computing system of claim 38 , wherein the carbon storage layer stores information by a phase change in the carbon storage layer.
47. The computing system of claim 38 , wherein the carbon storage layer stores information by formation of a conductive path in the carbon storage layer.