Integrated circuit including an ECC error counter

1. An integrated circuit comprising:

a memory array;

an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit;

a mimic circuit configured to provide a second signal indicating whether the first signal is valid;

a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error; and

an interface configured to output a count of the counter in response to a third signal and a clock signal.

2. The integrated circuit of claim 1 , further comprising:

a data pad or pin configured to receive the output count from the interface.

3. An integrated circuit comprising:

a memory array;

an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit;

a mimic circuit configured to provide a second signal indicating whether the first signal is valid; and

a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error,

wherein the mimic circuit provides a first delay equivalent to a first time to read data from the memory array plus a second delay equivalent to a second time for the ECC circuit to provide the first signal.

4. The integrated circuit of claim 3 , wherein the memory array comprises a dynamic random access memory (DRAM) array.

5. The integrated circuit of claim 3 , further comprising:

OR gates for combining error signals from a plurality of ECC column blocks within the ECC circuit to provide the first signal.

6. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a memory array;

an error correction code (ECC) circuit configured to provide a first signal in response to detecting an error in data read from the memory array in response to a column address strobe (CAS) signal;

a mimic circuit configured to delay the CAS signal to provide a second signal indicating whether the first signal is valid; and

a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.

7. The system of claim 6 , wherein the memory device further comprises:

a serial interface configured to serially output a count of the counter in response, to a test mode signal and a clock signal.

8. The system of claim 7 , wherein the memory device further comprises:

a data pad or pin configured to receive the count from the serial interface.

9. The system of claim 7 , wherein the memory device further comprises:

an off chip driver enable circuit configured to enable the data pad or pin in response to the test mode signal.

10. The system of claim 6 , wherein the mimic circuit provides a first delay equivalent to a first time to read data from the memory array plus a second delay equivalent to a second time for detecting an error in the data read from the memory array.

11. A method for testing a memory, the method comprising:

reading data from a memory array in response to a first signal;

checking the read data for an error;

providing a second signal in response to detecting an error in the read data;

delaying the first signal to provide a third signal indicating whether the second signal is valid; and

incrementing a counter in response to the third signal and the second signal.

12. The method of claim 11 , wherein checking the read data for an error comprises checking the read data for a single bit failure.

13. The method of claim 11 , further comprising:

outputting a count of the counter in response to a fourth signal.

14. The method of claim 13 , wherein outputting the count comprises serially outputting the count in response to the fourth signal and a clock signal.

15. The method of claim 13 , wherein outputting the count comprises outputting the count on a data pad or pin.

16. A method for testing a memory, the method comprising:

reading data from a memory array in response to a CAS signal;

checking the read data for an error;

providing an error signal in response to detecting an error in the read data;

correcting the read data in response to detecting the error;

delaying the CAS signal by a first delay equivalent to a first time for reading the data from the memory array and by a second delay equivalent to a second time for checking the read data for an error to provide a data ready signal indicating whether the error signal is valid; and

incrementing a counter in response to the data ready signal and the error signal.

17. The method of claim 16 , further comprising:

serially outputting a count of the counter on a data pad or pin in response to a test mode signal and a clock signal.

18. The method of claim 16 , wherein reading data from the memory array comprises reading data from a dynamic random access memory (DRAM) array.

19. The method of claim 16 , wherein checking the read data for an error comprises checking the read data for a parity error.

20. The method of claim 16 , wherein checking the read data for an error comprises checking the read data for a single bit failure.