Method and integrated circuit for determining the state of a resistivity changing memory cell

1. A method for determining the state of a resistivity changing memory cell, the method comprising:

detecting a first resistance of the resistivity changing memory cell;

determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value; and

initializing the resistivity changing memory cell into one of at least four resistivity changing memory states;

detecting a second resistance value of the resistivity changing memory cell;

determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value; and

determining the state of the resistivity changing memory cell using the first and the second result values.

2. The method according to claim 1 , wherein the resistivity changing memory cell comprises a first ferromagnetic layer structure, a non-ferromagnetic layer structure disposed above the first ferromagnetic layer structure and a second ferromagnetic layer structure disposed above the non-ferromagnetic layer structure.

3. The method according to claim 2 , wherein the first ferromagnetic layer structure and the second ferromagnetic layer structure comprise materials such as PtMn, CoFe, Ru, and NiFe.

4. The method according to claim 2 , wherein the non-ferromagnetic layer structure comprises Al 2 O 3 .

5. The method according to claim 2 , the second ferromagnetic layer structure having a magnetic switching threshold that is smaller than the magnetic switching threshold of the first ferromagnetic layer structure.

6. The method according to claim 5 , comprising initializing the resistivity changing memory cell by applying a magnetic field, the magnetic field being smaller than the magnetic switching threshold of the first ferromagnetic layer structure.

7. The method according to claim 1 , comprising storing the first result value in a first storing device.

8. The method according to claim 7 , wherein the first storing device is a latch.

9. The method according to claim 1 , comprising storing the second result value in a second storing device.

10. The method according to claim 9 , wherein the second storing device is a latch.

11. An integrated read circuit for determining the state of a resistivity changing memory cell, the circuit comprising:

a circuit configured to detect a first resistance of the resistivity changing memory cell;

a circuit configured to determine whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value;

a circuit configured to initialize the resistivity changing memory cell into one of at least four resistivity changing memory states;

a circuit configured to detect a second resistance value of the resistivity changing memory cell;

a circuit configured to determine whether the second resistance value is smaller than the predetermined threshold value determining a second result value; and

a circuit configured to determine the state of the resistivity changing memory cell using the first and the second result values.

12. The integrated circuit according to claim 11 , wherein the resistivity changing memory cell comprises a first ferromagnetic layer structure, a non-ferromagnetic layer structure disposed above the first ferromagnetic layer structure and a second ferromagnetic layer structure disposed above the non-ferromagnetic layer structure.

13. The integrated circuit according to claim 12 , wherein the resistivity changing memory cell comprises a magnetic tunnel junction.

14. A computing system comprising:

an input apparatus;

an output apparatus;

a processing apparatus;

the integrated circuit of claim 11 .

15. The computing system of claim 14 , wherein at least one of the input apparatus and the output apparatus comprises a wireless communication apparatus.