Clock signal synchronizing device with inherent duty-cycle correction capability
View Patent ↗One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.
1. A clock signal synchronizing device comprising:
a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal;
a negator for inverting the delayed clock signal to output an inverted delayed clock signal;
a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal;
a phase interpolator; and
a phase interpolator control circuit;
wherein the phase interpolator adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1; and
wherein the phase interpolator control circuit sets the value of p to substantially 0 when the incoming clock signal and the inverted delayed clock signal are not in phase, and sets the value of p to a value greater than 0 and smaller than or equal to 1 when the incoming clock signal and the inverted delayed clock signal are substantially in phase.
2. The clock signal synchronizing device of claim 1 , further comprising a further delay circuit having a constant delay time and being connected between the output of the delay circuit having a variable delay time and an input of the negator.
3. The clock signal synchronizing device of claim 1 , wherein the incoming clock signal is a differential clock signal.
4. The clock signal synchronizing device of claim 1 , wherein the variable delay time of the delay circuit is adjusted by respectively incrementing the variable delay time by a predetermined step until the incoming clock signal and the inverted delayed clock signal are in phase.
5. The clock signal synchronizing device of claim 1 , wherein the variable delay time of the delay circuit is adjusted by respectively decrementing the variable delay time by a predetermined step until the incoming clock signal and the inverted delayed clock signal are in phase.
6. The clock signal synchronizing device of claim 1 , wherein the delay circuit delays the compound signal;
the negator inverts the delayed compound signal; and
the phase interpolator adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed compound clock signal multiplied with a factor of substantially p to output a further compound signal to the delay circuit.
7. The clock signal synchronizing device of claim 6 , wherein the steps specified in claim 6 are carried out iteratively over a plurality of cycles to correct static duty-cycle offset of the incoming clock signal and to average out uncorrelated clock-jitter comprised in the incoming clock signal.
8. A clock signal synchronizing device comprising:
a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal;
a negator for inverting the delayed clock signal to output an inverted delayed clock signal;
a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal;
a phase interpolator;
wherein the phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.
9. The clock signal synchronizing device of claim 8 , further comprising a further delay circuit having a constant delay time and being connected between the output of the delay circuit having a variable delay time and an input of the negator.
10. The clock signal synchronizing device of claim 8 , wherein the incoming clock signal is a differential clock signal.
11. The clock signal synchronizing device of claim 8 , further comprising a phase interpolator control circuit connected to the phase interpolator, the phase interpolator control circuit generating a control signal comprising a value for the factor p being greater than 0 to activate the phase interpolator.
12. The clock signal synchronizing device of claim 8 , wherein the delay circuit delays the compound signal by the adjusted variable delay time;
the negator inverts the delayed compound signal; and
the phase interpolator adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed compound clock signal multiplied with a factor of substantially p to output a further compound signal to the delay circuit.
13. The clock signal synchronizing device of claim 12 , wherein the steps specified in claim 12 are carried out iteratively over a plurality of cycles to correct static duty-cycle offset of the incoming clock signal and to average out uncorrelated clock-jitter comprised in the incoming clock signal.
14. A clock signal synchronizing method for use in a clock signal synchronizing device comprising a delay control circuit connected to a delay circuit having a variable delay time, a negator, and a phase interpolator, the method comprising:
receiving an incoming clock signal;
delaying, by the delay circuit, the incoming clock signal or a signal generated therefrom to generate a delayed clock signal;
inverting, by the negator, the delayed clock signal to generate an inverted delayed clock signal;
controlling, by the delay control circuit, the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal; and
when the incoming clock signal and the inverted delayed clock signal are substantially in phase, adding, by the phase interpolator, the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.
15. The method of claim 14 , further comprising:
delaying, by the delay circuit, the compound signal;
inverting, by the negator, the delayed compound clock signal to generate an inverted delayed compound clock signal; and
adding, by the phase interpolator, the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed compound clock signal multiplied with a factor of substantially p to output a further compound signal to the delay circuit.
16. The method of claim 15 , wherein the steps specified in claim 15 are carried out iteratively over a plurality of cycles to correct static duty-cycle offset of the incoming clock signal and to average out uncorrelated clock-jitter comprised in the incoming clock signal.
17. The method of claim 14 , wherein the phase interpolator is caused to operate by a control signal comprising a value for the factor p being greater than 0.
18. The method of claim 14 , wherein the variable delay time of the delay circuit is adjusted by respectively incrementing the variable delay time by a predetermined step until the incoming clock signal and the inverted delayed clock signal are in phase.
19. The method of claim 14 , wherein the variable delay time of the delay circuit is adjusted by respectively decrementing the variable delay time by a predetermined step until the incoming clock signal and the inverted delayed clock signal are in phase.
20. Integrated circuit chip, comprising the clock signal synchronizing device of claim 1 .