Resistive memory including selective refresh operation

1. A memory comprising:

an array of phase change memory cells; and

a first circuit for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.

2. The memory of claim 1 , further comprising:

a second circuit for reading each memory cell within the array of phase change memory cells during a refresh operation to determine whether each memory cell is programmed to a non-crystalline state.

3. The memory of claim 1 , wherein the first circuit refreshes at least two memory cells within the array of phase change memory cells by consecutively resetting the at least two memory cells within a set operation time.

4. The memory of claim 1 , wherein the first circuit refreshes the memory cells by:

activating a word line to read a state of each memory cell on the word line;

reading the state of each memory cell on the word line and temporarily storing the state of each memory cell;

providing a write enable signal in response to each temporarily stored state which includes a non-crystalline state; and

refreshing a memory cell in response to each write enable signal.

5. The memory of claim 1 , wherein the array of phase change memory cells comprises an array of single bit phase change memory cells.

6. The memory of claim 1 , wherein the array of phase change memory cells comprises an array of multi-bit phase change memory cells.

7. A memory comprising:

an array of resistive memory cells;

a sense circuit configured for sensing a state of each memory cell in the array of resistive memory cells;

a write circuit configured for programming each memory cell in the array of resistive memory cells; and

a controller configured for controlling a refresh operation in which the sense circuit senses the state of each memory cell and the write circuit only refreshes the state of each memory cell sensed to be in a resistance state greater than a lowest resistance state.

8. The memory of claim 7 , wherein the sense circuit comprises buffers for temporarily storing the sensed state of each memory cell during a refresh operation, the buffers providing signals to the write circuit indicating which memory cells are in a resistance state greater than the lowest resistance state.

9. The memory of claim 7 , wherein the array of resistive memory cells comprises word lines and the refresh operation refreshes all memory cells on a word line in parallel.

10. The memory of claim 7 , wherein the write circuit refreshes at least two memory cells by consecutively resetting the at least two memory cells within a set operation time.

11. The memory of claim 7 , wherein the array of resistive memory cells comprises an array of single bit resistive memory cells.

12. The memory of claim 7 , wherein the array of resistive memory cells comprises an array of multilevel resistive memory cells.

13. The memory of claim 7 , wherein the array of resistive memory cells comprises an array of phase change memory cells.

14. A memory comprising:

an array of phase change memory cells; and

a circuit configured to refresh only memory cells in a non-crystalline state in response to a request for a refresh operation.

15. The memory of claim 14 , wherein the circuit is configured to refresh at least two memory cells in parallel.

16. The memory of claim 14 , wherein the circuit is configured to consecutively reset at least two memory cells within a set operation time.

17. The memory of claim 14 , wherein the array of phase change memory cells comprises an array of single bit phase change memory cells.

18. The memory of claim 14 , wherein the array of phase change memory cells comprises an array of multi-bit phase change memory cells.