Method for fabricating an integrated circuit including resistivity changing material having a planarized surface

1. A method for fabricating an integrated circuit, the method comprising:

providing a preprocessed wafer including a first electrode;

depositing a dielectric material over the preprocessed wafer;

etching an opening in the dielectric material to expose a portion of the first electrode;

depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode;

planarizing the first resistivity changing material to expose the etched dielectric material;

depositing a second resistivity changing material over the etched dielectric material and the planarized first resistivity changing material so that a top side of the planarized first resistivity changing material directly contacts a bottom side of the second resistivity changing material; and

depositing an electrode material over the second resistivity changing material.

2. The method of claim 1 , further comprising etching the electrode material and the second resistivity changing material to provide a second electrode and etched second resistivity changing material contacting the first resistivity changing material.

3. The method of claim 1 , wherein etching the opening comprises etching a pore.

4. The method of claim 1 , wherein etching the opening comprises etching a trench.

5. The method of claim 1 , wherein etching the opening comprises etching an opening having tapered sidewalls.

6. The method of claim 1 , wherein etching the opening comprises etching an opening having parallel sidewalls.

7. The method of claim 1 , wherein depositing the first resistivity changing material comprises depositing a first phase change material, and wherein depositing the second resistivity changing material comprises depositing a second phase change material.

8. The method of claim 7 , wherein the first and second phase change materials comprise different phase change materials.

9. The method of claim 7 , wherein the second phase change material has a lower thermal conductivity than the first phase change material.

10. The method of claim 7 , wherein the second phase change material is doped differently than the first phase change material.

11. The method of claim 10 , comprising doping the first phase change material with N and the second phase change material with at least one of SiN and SiO 2 .

12. A method for fabricating a memory, the method comprising:

providing a preprocessed wafer including a first electrode;

providing dielectric material having a pore exposing a portion of the first electrode over the preprocessed wafer;

depositing a first phase change material over exposed portions of the dielectric material and the first electrode;

planarizing the first phase change material to expose the dielectric material;

depositing a second phase change material over the exposed dielectric material and the planarized first phase change material so that a top side of the planarized first phase change material directly contacts a bottom side of the second phase change material;

depositing an electrode material layer over the second phase change material; and

etching the electrode material layer and the second phase change material to provide a second electrode and etched second phase change material contacting the planarized first phase change material.