IP Library Granted Patent US 7,838,860
Granted Patent B2
US 7,838,860 · App. 11/766,290 · Granted Nov 23, 2010

Integrated circuit including vertical diode

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Quick Facts
Patent No.
US 7,838,860
App. No.
11/766,290
Granted
Nov 23, 2010
Kind
B2
Abstract

An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.

Claims (91)

1. An integrated circuit comprising:

a vertical diode;

a first electrode coupled to the vertical diode;

a resistivity changing material coupled to the first electrode;

a second electrode coupled to the resistivity changing material; and

a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material,

wherein the first sidewall of the spacer directly contacts a sidewall of the second electrode.

2. The integrated circuit of claim 1 , wherein a second sidewall of the spacer is aligned with a sidewall of the diode and a second sidewall of the first electrode.

3. The integrated circuit of claim 1 , further comprising:

a silicide contact coupling the diode to the first electrode.

4. The integrated circuit of claim 1 , wherein the first electrode comprises an etch stop material layer contacting the spacer.

5. The integrated circuit of claim 1 , wherein the first electrode comprises a first electrode material coupled to the diode and a second electrode material contacting the resistivity changing material.

6. The integrated circuit of claim 1 , further comprising:

a word line coupled to the diode.

7. The integrated circuit of claim 1 , wherein the resistivity changing material comprises phase change material.

8. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a vertical diode including a first polarity region and a second polarity region;

a first electrode coupled to the second polarity region;

phase change material coupled to the first electrode;

a second electrode coupled to the phase change material; and

a spacer having a first sidewall directly contacting a first sidewall of the first electrode, a sidewall of the phase change material, and a sidewall of the second electrode.

9. The system of claim 8 , wherein a second sidewall of the spacer is aligned with a second sidewall of the first electrode and a sidewall of the diode.

10. The system of claim 8 , wherein the memory device further comprises:

a silicide contact contacting the second polarity region and the first electrode.

11. The system of claim 8 , wherein the memory device further comprises:

a write circuit configured to program the phase change element;

a sense circuit configured to read a state of the phase change element; and

a controller configured to control read and write operations of the phase change element.

12. A memory comprising:

a first polarity region;

a second polarity region contacting the first polarity region;

a first electrode coupled to the second polarity region;

phase change material coupled to the first electrode;

a second electrode coupled to the phase change material; and

a spacer having a first sidewall directly contacting a first sidewall of the first electrode, a sidewall of the phase change material, and a sidewall of the second electrode.

13. The memory of claim 12 , wherein a second sidewall of the spacer is aligned with a second sidewall of the first electrode, a sidewall of the second polarity region, and a sidewall of the first polarity region.

14. The memory of claim 12 , further comprising:

a silicide contact contacting the second polarity region and the first electrode.

15. The memory of claim 12 , wherein the first electrode comprises an etch stop material layer contacting the spacer.

16. The memory of claim 12 , wherein the first electrode comprises a first electrode material coupled to the second polarity region and a second electrode material contacting the resistive memory element.

17. An integrated circuit comprising:

a vertical diode;

a silicide contact contacting the vertical diode;

a first electrode coupled to the silicide contact;

a spacer having a first sidewall contacting a first sidewall of the first electrode;

a resistivity changing material coupled to the first electrode; and

a second electrode coupled to the resistivity changing material,

wherein a second sidewall of the spacer is aligned with a sidewall of the vertical diode and a second sidewall of the first electrode.

18. The integrated circuit of claim 17 , wherein the first electrode comprises an etch stop material layer contacting the spacer.

19. The integrated circuit of claim 18 , wherein the first electrode comprises a first electrode material contacting the silicide contact and the etch stop material layer and a second electrode material contacting the resistivity changing material and the etch stop material layer.

20. The integrated circuit of claim 17 , wherein the first electrode comprises a first electrode material contacting the silicide contact and a second electrode material contacting the resistivity changing material.

21. The integrated circuit of claim 17 , further comprising:

a word line coupled to the diode.

22. The integrated circuit of claim 17 , wherein the resistivity changing material comprises phase change material.

23. The integrated circuit of claim 17 , further comprising:

at least one encapsulation material layer encapsulating the resistivity changing material and the second electrode.

24. An integrated circuit comprising:

a vertical diode;

a first electrode coupled to the vertical diode;

a resistivity changing material coupled to the first electrode;

a second electrode coupled to the resistivity changing material; and

a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material,

wherein a second sidewall of the spacer is aligned with a sidewall of the diode and a second sidewall of the first electrode.

25. The integrated circuit of claim 24 , wherein the first sidewall of the spacer contacts a sidewall of the second electrode.

26. The integrated circuit of claim 24 , further comprising:

a silicide contact coupling the diode to the first electrode.

27. The integrated circuit of claim 24 , wherein the first electrode comprises a first electrode material coupled to the diode and a second electrode material contacting the resistivity changing material.

28. The integrated circuit of claim 24 , further comprising:

a word line coupled to the diode.

29. The integrated circuit of claim 24 , wherein the resistivity changing material comprises phase change material.

30. An integrated circuit comprising:

a word line;

a vertical diode directly contacting the word line;

a silicide contact directly contacting the vertical diode;

a first electrode directly contacting the silicide contact;

a phase change material directly contacting the first electrode;

a second electrode directly contacting the phase change material; and

a spacer having a first sidewall directly contacting a first sidewall of the first electrode, a sidewall of the phase change material, and a sidewall of the second electrode,

wherein the spacer has a second sidewall opposite the first sidewall of the spacer, the second sidewall of the spacer aligned with a second sidewall of the first electrode, a sidewall of the silicide contact, and a sidewall of the diode.

31. The integrated circuit of claim 30 , wherein the second sidewall of the spacer is aligned with the sidewall of the word line.

32. The integrated circuit of claim 31 , further comprising:

a dielectric material having a sidewall directly contacting the second sidewall of the spacer, the second sidewall of the first electrode, the sidewall of the silicide contact, the sidewall of the diode, and the sidewall of the word line.

33. The integrated circuit of claim 30 , further comprising:

a dielectric material having a sidewall directly contacting the second sidewall of the spacer, the second sidewall of the first electrode, the sidewall of the silicide contact, and the sidewall of the diode.

34. The integrated circuit of claim 30 , wherein the phase change material comprises at least one Ge, Sb, Te, Ga, As, In, Se, and S.

35. The integrated circuit of claim 30 , further comprising:

a write circuit configured to program the phase change material;

a sense circuit configured to read a state of the phase change material; and

a controller configured to control read and write operations of the phase change material.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: QIMONDA NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 026138/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2007
From: HAPP, THOMAS; PHILIPP, JAN BORIS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 019655/0836 →