Memory cell arrangements

1. A memory cell arrangement, comprising:

a first memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells;

a second memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells;

dielectric material between and above the plurality of transistors of the first memory cell string and the plurality of transistors of the second memory cell string;

a source/drain line groove in the dielectric material, the source/drain line groove extending from a source/drain region of one transistor of the plurality of transistors of the first memory cell string to a source/drain region of one transistor of the plurality of transistors of the second memory cell string;

electrically conductive filling material in the source/drain line groove coupled to the source/drain region of the transistor of the plurality of transistors of the first memory cell string and to the source/drain region of the transistor of the plurality of transistors of the second memory cell string; and

dielectric filling material in the source/drain line groove between the source/drain region of the transistor of the plurality of transistors of the first memory cell string and the source/drain region of the transistor of the plurality of transistors of the second memory cell string.

2. The memory cell arrangement of claim 1 , wherein the first memory cell string comprises a NAND memory cell string.

3. The memory cell arrangement of claim 2 , wherein the second memory cell string comprises a NAND memory cell string.

4. The memory cell arrangement of claim 1 , wherein the transistor of the plurality of transistors of the first memory cell string comprises a select transistor selecting the memory cells of the first memory cell string.

5. The memory cell arrangement of claim 4 , wherein the transistor of the plurality of transistors of the second memory cell string comprises a select transistor selecting the memory cells of the second memory cell string.

6. The memory cell arrangement of claim 1 , wherein the transistor of the plurality of transistors of the first memory cell string comprises a memory cell of the first memory cell string.

7. The memory cell arrangement of claim 6 , wherein the transistor of the plurality of transistors of the second memory cell string comprises a memory cell of the second memory cell string.

8. The memory cell arrangement of claim 6 , wherein the memory cells comprise non-volatile memory cells.

9. The memory cell arrangement of claim 8 , wherein the non-volatile memory cells comprise floating gate memory cells.

10. The memory cell arrangement of claim 8 , wherein the non-volatile memory cells comprise charge trapping memory cells.

11. The memory cell arrangement of claim 1 , wherein the memory cells comprise non-volatile memory cells.

12. The memory cell arrangement of claim 11 , wherein the non-volatile memory cells comprise floating gate memory cells.

13. The memory cell arrangement of claim 11 , wherein the non-volatile memory cells comprise charge trapping memory cells.

14. The memory cell arrangement of claim 1 , wherein the electrically conductive filling material comprises a metal.

15. The memory cell arrangement of claim 14 , wherein the metal comprises a material selected from the group consisting of titanium, titanium and nitride, or tungsten.

16. The memory cell arrangement of claim 1 , wherein the dielectric filling material comprises an oxide.

17. The memory cell arrangement of claim 1 , further comprising:

a first bit line coupled to the electrically conductive filling material that is coupled to the source/drain region of the transistor of the plurality of transistors of the first memory cell string; and

a second bit line coupled to the electrically conductive filling material that is coupled to the source/drain region of the transistor of the plurality of transistors of the second memory cell string.

18. The memory cell arrangement of claim 17 , wherein the first bit line and the second bit line are made of a metal.

19. The memory cell arrangement of claim 17 , further comprising

a further source/drain line groove in the dielectric material, the source/drain line groove extending from a source/drain region of a further transistor of the plurality of transistors of the first memory cell string to a source/drain region of a further transistor of the plurality of transistors of the second memory cell string;

further electrically conductive filling material in the further source/drain line groove coupled to the source/drain region of the further transistor of the plurality of transistors of the first memory cell string and to the source/drain region of the further transistor of the plurality of transistors of the second memory cell string; and

a source line coupled to the further electrically conductive filling material.

20. The memory cell arrangement of claim 19 , wherein the further electrically conductive filling material is made of the same material as the electrically conductive filling material.

21. The memory cell arrangement of claim 17 , wherein a source line is made of the same material as the first bit line and the second bit line.

22. The memory cell arrangement of claim 18 , wherein the metal has a resistivity of less than about 10 μΩcm.

23. The memory cell arrangement of claim 18 , wherein the metal comprises a metal selected from the group consisting of copper, aluminum, silver, and gold.

24. The memory cell arrangement of claim 22 , wherein the metal has a resistivity of less than or equal to 6 μΩcm.

25. The memory cell arrangement of claim 24 , wherein the metal has a resistivity of less than or equal to 5 μΩcm.

26. The memory cell arrangement of claim 1 , further comprising a source line coupled to the electrically conductive filling material that is coupled to the source/drain region of the transistor of the plurality of transistors of the first memory cell string.