Integrated circuit having a resistive switching device
View Patent ↗An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode.
1. An integrated circuit having a resistively switching memory comprising:
a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode;
a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode;
the second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; and
wherein the second electrode comprises a buried electrode at least partially positioned below the bitline electrode and the third electrode.
2. The integrated circuit of claim 1 , comprising wherein a wordline is connected to a gate of the selection transistor.
3. The integrated circuit of claim 2 , comprising wherein the wordline is connected to a gate of the connection transistor.
4. The integrated circuit of claim 2 , comprising wherein another wordline is connected to a gate of the connection transistor.
5. The integrated circuit of claim 1 , comprising wherein at least one out of the selection transistor and the connection transistor is a vertical transistor at least partially guiding a substantially vertical current flow.
6. The integrated circuit of claim 1 , comprising wherein a further switching active volume and the connection transistor are connected in series between the second electrode and the third electrode.
7. The integrated circuit of claim 1 , comprising wherein the bitline electrode and the third electrode are at least partially positioned above a substrate and the second electrode is positioned within the substrate.
8. The integrated circuit of claim 7 , comprising wherein the second electrode comprises doped silicon.
9. The integrated circuit of claim 1 , comprising wherein a form of at least one out of the second electrode and the third electrode comprises at least one of a group consisting of a plate, a line, and a mesh.
10. The integrated circuit of claim 1 , comprising wherein the connection transistor and the selection transistor are at least partially manufactured using the same processes.
11. The integrated circuit of claim 10 , comprising wherein a wordline connected to a gate of the connection transistor and a wordline connected to a gate of the selection transistor are manufactured simultaneously.
12. The integrated circuit of claim 1 , comprising wherein the switching active volume comprises a phase change element.
13. The integrated circuit of claim 1 , comprising wherein the connection transistor is activated when the selection transistor is activated.
14. The integrated circuit of claim 13 , comprising wherein the connection transistor is always activated during operation of the memory cell.
15. A memory device comprising:
a plurality of resistively switching memory cells, each of the resistively switching memory cells comprising:
a bitline electrode and a second electrode common to the set of memory cells having a lower voltage potential than the bitline electrode;
a switching active volume and a selection transistor connected in series between the respective bitline electrode and the common second electrode;
wherein the common second electrode comprises a buried electrode at least partially positioned below each bitline electrode and the third electrode; and
wherein the common second electrode is connected, via at least one associated connection transistor, to a third electrode having the same or a lower voltage potential than the common second electrode.
16. The memory device of claim 15 , comprising wherein a same wordline is connected to a gate of at least one of the selection transistors and a gate of one of the connection transistors.
17. The memory device of claim 15 , comprising wherein a same wordline is connected to gates of a plurality of the connection transistors.
18. The memory device of claim 17 , comprising wherein the wordline connected to the gates of the plurality of the connection transistors is different from a respective wordline of associated selection transistors, and wherein the respective wordlines of the associated selection transistors are each different wordlines.
19. The memory device of claim 15 , comprising wherein at least one out of the selection transistors and the connection transistors is a vertical transistor at least partially having a substantially vertical current flow.
20. The memory device of claim 15 , comprising wherein a further switching active volume and the connection transistor are connected in series between the second electrode and the third electrode.
21. The memory device of claim 15 , comprising wherein the bitline and third electrodes are positioned above a substrate and the second electrode is positioned within the substrate.
22. The memory device of claim 21 , wherein the second electrodes comprises doped silicon.
23. The memory device of claim 15 , wherein a form of at least one out of the second electrodes and the third electrodes comprises at least one out a group comprising a plate, a line, and a mesh.
24. The memory device of claim 15 , comprising wherein the connection transistors and the selection transistors are at least partially manufactured using the same processes.
25. The memory device of claim 24 , comprising wherein the wordlines are manufactured simultaneously.
26. The memory device of claim 15 , wherein the switching active volumes comprises phase change elements.
27. The memory device of claim 15 , comprising wherein the connection transistors are activated during operation of the selection transistors.
28. The memory device of claim 27 , comprising wherein the connection transistors are always activated during operation of the memory device.
29. A method of operating an integrated circuit having a resistively switching memory cell comprising:
a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode;
a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode;
wherein the second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode;
wherein the second electrode comprises a buried electrode at least partially positioned below the bitline electrode and the third electrode,
wherein the method comprises:
activating the selection transistor to allow a current flow between the bitline electrode and the second electrode through the switching active volume;
activating the connection transistor such that it selectively allows a current flow between the second and third electrodes;
such that, by simultaneously activating the selection transistor and the connection transistor, a current can flow from the bitline electrode to the third electrode.
30. The method of claim 29 , wherein simultaneously activating the selection transistor and the connection transistor comprises permanently activating the connection transistor.
31. The method of claim 30 , comprising wherein the activating of the selection transistor and the active connection is performed by a same wordline.
32. The method of claim 30 , comprising wherein the activating of the selection transistor and the active connection is performed by different wordlines.
33. The method of claim 30 , comprising wherein a current through the transistors is flowing at least partially in a substantially vertical manner.
34. A method of operating a memory device comprising a plurality of resistively switching memory cells, each of the resistively switching memory cells comprising:
a bitline electrode and a second electrode common to the set of memory cells having a lower voltage potential than the bitline electrode;
a switching active volume and a selection transistor connected in series between the respective bitline electrode and the common second electrode;
wherein the common second electrode is connected, via at least one associated connection transistor, to a third electrode having the same or a lower voltage potential than the common second electrode;
wherein the common second electrode comprises a buried electrode at least partially positioned below each bitline electrode and the third electrode,
wherein the method comprises:
activating the selection transistor of one of the memory cells to allow a current flow between the bitline electrode and the common second electrode through the active volume;
activating the connection transistor of one of the memory cells such that the connection transistor selectively allows a current flow between the second and third electrodes;
such that by simultaneously activating the selection transistor and the connection transistor of one of the memory cells a current can flow from the bitline electrode to the third electrode.
35. The method of claim 34 , comprising simultaneously activating the selection transistor and the connection transistor comprises permanently activating the connection transistor.
36. The method of claim 34 , comprising performing the activating of the selection transistor and the active connection by a same wordline.
37. The method of claim 34 , comprising performing the activating of the selection transistor and the active connection by different wordlines.
38. The method of claim 34 , comprising wherein a current through the transistors is flowing at least partially in a substantially vertical manner.
39. A resistively switching memory cell of a memory device, the resistively switching memory cell comprising:
a first electrical connection means and a second electrical connection means having a lower voltage potential than the first electrical connection means;
a switching active means and a selection means for selectively allowing a current flowing through it connected in series between the fist electrical connection means and the second electrical connection means;
wherein the second electrical connection means is connected, via a connection means for selectively allowing a current flowing through it, to a third electrical connection means having the same or a lower voltage potential than the second electrical connection means;
wherein the second electrical connection means comprises a buried electrode at least partially positioned below the first electrical connection means and the third electrical connection means.
40. The memory cell of claim 39 , comprising wherein an electrical control means is connected to a control input of the selection means.
41. The memory cell of claim 39 , comprising wherein the same electrical control means is connected to a control input of the connection means.
42. The memory cell of claim 39 , comprising wherein a further electrical control means is connected to a control input of the connection means.