System and method for addressing errors in a multiple-chip memory device

1. A method of operating a multiple-chip memory device having a volatile memory element, comprising:

powering up the multiple-chip memory device;

reading initial repair information from a non-volatile memory in the multiple-chip memory device, the initial repair information, identifying one or more errors in a volatile memory element in the multiple-chip memory device;

decoding the initial repair information to generate volatile repair information;

storing the volatile repair information in a volatile repair information storage element;

receiving logical address information identifying a logical memory location in a volatile memory element after storing the volatile repair information;

reading the volatile repair information from the volatile repair information storage element;

generating physical address information identifying a physical memory location in the volatile memory element based on the logical address information and the volatile repair information;

wherein the volatile memory element repair information includes a plurality of repair items, each repair item including: one or more control bits indicating operations parameters of an identified error, and a plurality of address bits identifying one a row in the volatile memory element and a column in the volatile memory element.

2. The method of claim 1 , wherein the reading of the volatile memory element repair information is performed by reading saved volatile memory data including repair information from the non-volatile memory element.

3. The method of claim 1 , wherein each repair item further includes one or more bank bits identifying a memory bank in the volatile memory element.

4. A method of operating a multiple-chip memory device having a volatile memory element, comprising:

powering up the multiple-chip memory device;

reading initial repair information from a non-volatile memory in the multiple-chip memory device, the initial repair information identifying one or more errors in a volatile memory element in the multiple-chip memory device;

decoding the initial repair information to generate volatile repair information;

storing the volatile repair information in a volatile repair information storage element;

receiving logical address information identifying a logical memory location in a volatile memory element after storing the volatile repair information;

reading the volatile repair information from the volatile repair information storage element;

generating physical address information identifying a physical memory location in the volatile memory element based on the logical address information and the volatile repair information; and

further comprising reading volatile memory element operational information from a non-volatile memory in the multiple-chip memory device, the volatile memory element operational information identifying at least one operational parameter in the volatile memory element.

5. An apparatus for operating a multiple-chip memory device having a volatile memory element, comprising:

means for powering up the multiple-chip memory device;

means for reading initial repair information from a non-volatile memory in the multiple-chip memory device, the initial repair information identifying one or more errors in a volatile memory element in the multiple-chip memory device;

means for decoding the initial repair information to generate volatile repair information;

means for storing the volatile repair information in a volatile repair information storage element;

means for receiving logical address information identifying a logical memory location in a volatile memory element after the means for storing stores the volatile repair information;

means for reading the volatile repair information from the volatile repair information storage element;

means for generating physical address information identifying a physical memory location in the volatile memory element based on the logical address information and the volatile repair information; and

wherein the volatile memory element repair information includes a plurality of repair items, each repair item including: one or more control bits indicating operations parameters of an identified error, and a plurality of address bits identifying one a row in the volatile memory element and a column in the volatile memory element.

6. The apparatus of claim 5 , wherein the means for storing the volatile repair information performs the reading of the volatile memory element repair information by reading saved volatile memory data including repair information from the non-volatile memory element.

7. An apparatus for operating a multiple-chip memory device having a volatile memory element, comprising:

means for powering up the multiple-chip memory device;

means for reading initial repair information from a non-volatile memory in the multiple-chip memory device, the initial repair information identifying one or more errors in a volatile memory element in the multiple-chip memory device;

means for decoding the initial repair information to generate volatile repair information;

means for storing the volatile repair information in a volatile repair information storage element;

means for receiving logical address information identifying a logical memory location in a volatile memory element after the means for storing stores the volatile repair information;

means for reading the volatile repair information from the volatile repair information storage element;

means for generating physical address information identifying a physical memory location in the volatile memory element based on the logical address information and the volatile repair information; and

further comprising a means for reading volatile memory element operational information from a non-volatile memory in the multiple-chip memory device, the volatile memory element operational information identifying at least one operational parameter in the volatile memory element.