Methods and apparatuses for generating a random sequence of commands for a semiconductor device

1. A method of generating a random sequence of commands for a semiconductor device, the method comprising:

generating, via a computer, random state transitions within a finite state machine model of the semiconductor device;

determining, via the computer, a sequence of commands which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device;

determining, via the computer, minimum timing conditions for the commands of the sequence of commands; and

generating, via the computer, time stamps for the commands of the sequence of commands based on the determined minimum timing conditions.

2. The method of claim 1 , comprising determining the minimum timing conditions using a command-to-command delay table.

3. The method of claim 1 , comprising generating the random state transitions using at least one of a state transition table and a state transition probability table.

4. A method of generating a random pattern for at least one of simulation and test of a semiconductor device, the method comprising:

generating, via a computer, random state transitions within a state machine model of the semiconductor device;

determining, via the computer, a sequence of commands which are associated to the generated random state transitions based on the state machine model of the semiconductor device;

determining, via the computer, minimum timing conditions for the commands of the sequence of commands;

generating, via the computer, timings for the commands of the sequence of commands based on the determined minimum timing conditions; and

generating, via the computer, a pin-specific pattern based on the sequence of commands and the timings for the commands of the sequence of commands by using a command truth table.

5. The method of claim 4 , comprising generating the random state transitions using at least one of a state transition table and a state transition probability table.

6. The method of claim 5 , further comprising:

modifying the pin-specific-pattern such that, additionally, signal levels are applied to non-activated pins when at least one of testing and simulating the semiconductor device.

7. The method of claim 4 , comprising determining the minimum timing conditions using a command-to-command delay table.

8. The method of claim 4 , comprising determining the timings for the commands of the sequence of commands based on the determined minimum timing conditions for the commands of the sequence of commands and additional random time intervals.

9. The method of claim 8 , wherein the additional random time intervals comprise a decreasing probability distribution.

10. The method of claim 4 , further comprising:

generating random data topologies for a memory test of the semiconductor device.

11. A physical computer program product used for storing instructions for generating a random sequence of commands for at least one of simulation and test of a semiconductor device, wherein the computer program product instructions causes the following actions when executed on a computer:

generating random state transitions within a finite state machine model of the semiconductor device;

determining a sequence of commands which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device;

determining minimum timing conditions for the commands of the sequence of Commands; and

generating time stamps for the commands of the sequence of commands based on the determined minimum timing conditions.

12. The computer program product of claim 11 , wherein the computer program product instructions further causes the following action when executed on a computer:

generating a pin-specific pattern based on the sequence of commands and the time stamps for the commands of the sequence of commands by using a command truth table.

13. An apparatus comprising:

a sequence generator configured to generate random state transitions within a finite state machine model of a semiconductor device;

a timing generator configured to determine a sequence of commands which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device;

wherein the apparatus is further configured to determine minimum timing conditions for the commands of the sequence of commands; and

wherein the apparatus is further configured to determine the minimum timing conditions by using a command-to-command delay table.

14. The apparatus of claim 13 , wherein the apparatus is further configured to generate the random state transitions by using at least one of a state transition table and a state transition probability table.

15. The apparatus of claim 13 , wherein the apparatus is adapted to generate a random sequence of commands for at least one of simulation and test of a semiconductor device.

16. An apparatus comprising:

a sequence generator configured to generate random state transitions within a finite state machine model of a semiconductor device;

a timing generator configured to determine a sequence of commands which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device;

wherein the apparatus is further configured to determine minimum timing conditions for the commands of the sequence of commands; and

wherein the apparatus is further configured to generate time stamps for the commands of the sequence of commands based on the determined minimum timing conditions.

17. The apparatus of claim 16 , wherein the apparatus is further configured to generate the random state transitions by using at least one of a state transition table and a state transition probability table.

18. The apparatus of claim 16 , wherein the apparatus is adapted to generate a random sequence of commands for at least one of simulation and test of a semiconductor device.

19. An apparatus comprising:

a random command sequence generator configured to generate random state transitions within a state machine model of a semiconductor device and determine a sequence of commands which are associated to the generated random state transitions;

a timing generator configured to determine minimum timing conditions for the commands of the sequence of commands and generate timings for the commands based on the minimum timing conditions of the commands; and

a pin-specific pattern generator configured to generate a pin-specific pattern based on the sequence of commands and the timings using a command truth table.

20. The apparatus of claim 19 , wherein the apparatus is further configured to generate the random state transitions by using at least one of a state transition table and a state transition probability table.

21. The apparatus of claim 19 , wherein the apparatus is further configured to determine the minimum timing conditions by using a command-to-command delay table, configured to generate a random pattern for at least one of simulation and test of a semiconductor device, and configured to generate a random sequence of commands for at least one of simulation and test of the semiconductor device.