Integrated circuit including diode memory cells

1. An integrated circuit comprising:

a transistor formed in a substrate;

a contact coupled to the transistor;

a first diode resistivity changing material memory cell coupled to the contact; and

a second diode resistivity changing material memory cell coupled to the contact,

wherein the first diode resistivity changing material memory cell is positioned between the second diode resistivity changing material memory cell and the substrate.

2. The integrated circuit of claim 1 , wherein the first diode resistivity changing material memory cell comprises:

a polysilicon diode; and

a resistivity changing material coupled to the polysilicon diode.

3. The integrated circuit of claim 1 , wherein the first diode resistivity changing material memory cell comprises a first diode phase change memory cell.

4. The integrated circuit of claim 1 , wherein the transistor comprises a field effect transistor.

5. The integrated circuit of claim 1 , further comprising:

a first bit line coupled to the first diode resistivity changing material memory cell;

a second bit line coupled to the second diode resistivity changing material memory cell;

a word line coupled to a gate of the transistor; and

a ground line coupled to the transistor opposite the contact.

6. The integrated circuit of claim 5 , wherein the word line is parallel to the ground line.

7. The integrated circuit of claim 5 , wherein the first bit line and the second bit line are parallel to the ground line.

8. The integrated circuit of claim 5 , wherein the first bit line and the second bit line are perpendicular to the word line, and

wherein the ground line is diagonal to the first bit line, the second bit line, and the word line.

9. An integrated circuit comprising:

an access transistor formed in a substrate;

a vertical contact coupled to the transistor;

a first diode resistive memory cell coupled to the vertical contact; and

a second diode resistive memory cell coupled to the vertical contact,

wherein the first diode resistive memory cell is located between the second diode resistive memory cell and the substrate.

10. The integrated circuit of claim 9 , wherein the first diode resistive memory cell comprises a first polysilicon diode, and

wherein the second diode resistive memory cell comprises a second polysilicon diode.

11. The integrated circuit of claim 9 , wherein the transistor comprises a field effect transistor.

12. The integrated circuit of claim 9 , further comprising:

a third diode resistive memory cell coupled to the vertical contact,

wherein the second diode resistive memory cell is located between the third diode resistive memory cell and the substrate.

13. The integrated circuit of claim 9 , wherein the first diode resistive memory cell comprises a first diode phase change memory cell, and

wherein the second diode resistive memory cell comprises a second diode phase change memory cell.

14. The integrated circuit of claim 9 , further comprising:

a first bit line coupled to the first diode resistive memory cell;

a second bit line coupled to the second diode resistive memory cell;

a word line coupled to a gate of the transistor; and

a ground line coupled to the transistor opposite the contact.

15. The integrated circuit of claim 14 , wherein the word line is parallel to the ground line.

16. The integrated circuit of claim 14 , wherein the first bit line and the second bit line are parallel to the ground line.

17. The integrated circuit of claim 14 , wherein the first bit line and the second bit line are perpendicular to the word line, and

wherein the ground line is diagonal to the first bit line, the second bit line, and the word line.

18. An integrated circuit comprising:

a first diode;

a first phase change element coupled to the first diode;

a second diode;

a second phase change element coupled to the second diode; and

a transistor configured to access the first phase change element and the second phase change element,

wherein the second diode and the second phase change element are stacked over the first diode and the first phase change element.

19. The integrated circuit of claim 18 , further comprising:

a vertical contact electrically coupled to the transistor, the first diode, and the second diode.

20. The integrated circuit of claim 19 , further comprising:

a first metal pad electrically coupling the vertical contact to the first diode, the first metal pad perpendicular to the vertical contact; and

a second metal pad electrically coupling the vertical contact to the second diode, the second metal pad perpendicular to the vertical contact.

21. The integrated circuit of claim 18 , wherein the first phase change element comprises:

a first electrode;

a second electrode; and

phase change material contacting the first electrode and the second electrode, the phase change material having a greater cross-sectional width than the first electrode.

22. The integrated circuit of claim 18 , wherein the first phase change element comprises:

a first ring electrode;

a second electrode; and

phase change material contacting the first ring electrode and the second electrode.

23. The integrated circuit of claim 18 , wherein the first phase change element comprises:

a first electrode;

a second electrode; and

phase change material contacting the first electrode and the second electrode, the phase change material including tapered sidewalls.

24. The integrated circuit of claim 18 , further comprising:

a first bit line coupled to the first phase change element;

a second bit line coupled to the second phase change element;

a word line coupled to a gate of the transistor; and

a ground line coupled to a source-drain path of the transistor.

25. The integrated circuit of claim 24 , wherein the word line is parallel to the ground line.

26. The integrated circuit of claim 24 , wherein the first bit line and the second bit line are parallel to the ground line.

27. The integrated circuit of claim 24 , wherein the first bit line and the second bit line are perpendicular to the word line, and

wherein the ground line is diagonal to the first bit line, the second bit line, and the word line.