Integrated circuit including a capacitor and method

1. An integrated circuit including a capacitor comprising:

a first electrode comprising a plurality of conductive lines separated from each other and being configured to be held at a potential being the same for all conductive lines; and

a second electrode enclosing individual ones of the conductive lines at a top side and at least one lateral side and being separated from the first electrode by a dielectric layer, the second electrode comprising a polycrystalline semiconductor material, a metal or a metal-semiconductor compound; and

a contact line extending across the plurality of conductive lines, the contact line electrically coupled to the plurality of conductive lines of the first electrode and electrically insulated from the second electrode.

2. The integrated circuit of claim 1 , comprising wherein the conductive lines of the first electrode are formed above a surface of a substrate.

3. The integrated circuit of claim 2 , comprising wherein the conductive lines are separated from each other by trenches extending into the substrate and being partially filled with an insulating material.

4. The integrated circuit of claim 2 , comprising wherein the substrate is a semiconductor substrate and wherein the first electrode comprises doped substrate portions.

5. The integrated circuit of claim 1 , wherein the dielectric layer comprises a material or a layer stack of materials selected from a group comprising semiconductor oxides, semiconductor nitrides, or high-k dielectrics.

6. The integrated circuit of claim 1 , comprising:

wherein the conductive lines of the first electrode comprise polysilicon, are formed above a semiconductor substrate and are separated from the semiconductor substrate by a gate oxide layer;

the conductive lines are separated from each other by trenches extending into the semiconductor substrate and being filled with an insulating material extending above a surface of the substrate, a trench width of individual ones of the trenches being equal to a line width of individual ones of the conductive lines;

the dielectric layer is formed conformal on the top and the lateral sides of the conductive lines and on top of the insulating material within the trenches and comprises a layer stack of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer; and

the second electrode is formed above and in the trenches between the conductive lines of the first electrode and comprises polysilicon.

7. A method of manufacturing an integrated circuit including a capacitor comprising:

patterning a first conductive layer to form separate conductive lines;

electrically connecting the conductive lines to form a first electrode of the capacitor;

forming a second electrode of the capacitor in a second conductive material;

forming a dielectric layer between the first and the second electrode of the capacitor;

forming the dielectric layer on a top side and on lateral sides of the conductive lines;

forming the second conductive material above and in the spaces between the conductive lines;

removing the dielectric layer from a section of the first conductive layer; and

patterning the second conductive material to form the second electrode of the capacitor and to form a contact to the first conductive layer.

8. The method of claim 7 , comprising forming the first conductive layer above a surface of a substrate.

9. The method of claim 8 , wherein patterning the first conductive layer comprises etching trenches reaching through the first conductive layer into the substrate.