IP Library Granted Patent US 7,794,614
Granted Patent B2
US 7,794,614 · App. 11/754,813 · Granted Sep 14, 2010

Methods for generating sublithographic structures

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Quick Facts
Patent No.
US 7,794,614
App. No.
11/754,813
Granted
Sep 14, 2010
Kind
B2
Abstract

One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Claims (44)

1. A method of forming a structure in a substrate, the method comprising:

forming a sidewall structure on a mask layer covering the substrate defining a first pattern of an exposed top surface of the mask layer;

forming an irradiated area in the mask layer by irradiating the first pattern;

removing the sidewall structure;

after removing the sidewall structure, forming a second pattern on the mask layer using a cut mask at least partially covering the irradiated area, the second pattern not including sidewall structures and different than the first pattern;

etching areas in the mask layer not covered with the second pattern;

removing the second pattern; and

removing the non-irradiated area of the mask layer.

2. The method according to claim 1 , wherein irradiating comprises irradiating normal to a substrate surface.

3. The method according to claim 1 , wherein the sidewall structure is used as a shadowing structure of the irradiation.

4. The method according to claim 1 , wherein irradiating is performed before forming the second pattern.

5. The method according to claim 1 , wherein the substrate comprises a wafer, a silicon wafer, a germanium wafer, a III-V material wafer, a structured wafer, a structured silicon wafer, a structured germanium wafer, or a structured III-V material wafer.

6. The method according to claim 1 , wherein the irradiating comprises at least the irradiating with ions, atoms or electrons.

7. The method according to claim 6 , wherein the irradiating comprises irradiating with helium atoms, argon atoms or xenon atoms.

8. The method according to claim 1 , wherein the irradiating comprises performing an ion implantation.

9. The method according to claim 8 , wherein the ion implantation comprises implanting ions selected from the group consisting of boron, oxygen, nitrogen and phosphorus.

10. The method according to claim 1 , wherein the non-irradiated area is removed at least partially by a selective etch process.

11. The method according to claim 10 , wherein the mask layer comprises silicon and a non-irradiated portion of the mask layer is selectively etched by wet chemistry comprising one of NH 4 OH and KOH.

12. The method according to claim 1 , wherein an irradiated area of the mask layer is at least partially removed after the irradiating.

13. The method according to claim 12 , wherein the irradiated area is removed at least partially by an etch process.

14. The method according to claim 1 , wherein the second pattern is formed before the irradiation step.

15. The method according to claim 1 , wherein the sidewall structure comprises a material selected from the group consisting of nitride, oxide, silicon, carbon, aluminum oxide and titanium oxide.

16. The method according to claim 1 , wherein at least one carrier structure for the at least one sidewall structure comprises at least one of the group of silicon, single layer resist, bilayer resist, multilayer resist and carbon.

17. The method according to claim 1 , wherein the sidewall structure is a spacer structure.

18. The method according to claim 17 , wherein the spacer structure is a sublithographic structure.

19. The method according to claim 17 , wherein the spacer structure has a width between 5 nm and 50 nm.

20. The method according to claim 1 , wherein the sidewall structure is manufactured by a spacer technique comprising a line-by-spacer technique, a pattern-by-spacer technique, a line-by-fill technique, a pattern-by-fill technique, a liner-fill or a pattern-fill technique.

21. The method according to claim 1 , wherein the mask layer comprises at least one layer selected from the group consisting of a hard mask layer, a silicon layer, a silicon oxynitride layer, an oxide layer, a nitride layer, a carbon layer, and an Al 2 O 3 layer.

22. A method of manufacturing a structure on or in a substrate, the method comprising:

positioning at least one spacer structure by a spacer technique on the substrate;

using the at least one spacer structure as a mask for at least one subsequent implantation step for generating at least one latent image in the substrate;

removing the at least one spacer structure;

after removing the at least one spacer structure forming a pattern not including a spacer structure using a cut mask, wherein the pattern at least partially covers the area with the latent image;

at least partially etching areas not covered with the pattern; and

removing the pattern at least partially.

23. A method of manufacturing a structure on or in a substrate, the method comprising:

positioning at least one spacer structure by a spacer technique on the substrate;

etching the substrate at least partially using the spacer structure as a mask;

generating a latent image in the substrate using the structure generated with the spacer structure as the mask in a subsequent implantation step;

removing the at least one spacer structure;

after removing the at least one spacer structure forming a pattern not including a spacer structure using a cut mask, wherein the pattern at least partially covers the area with the latent image;

etching at least partially areas not covered with the pattern;

removing the pattern at least partially; and

removing the implanted areas at least partially.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →