Sender, receiver and method of transferring information from a sender to a receiver
View Patent ↗Embodiments of the invention provide methods and apparatus for transferring information from a sender to a receiver, a symbol is selected out of a plurality of symbols representing the information, wherein each of the plurality of symbols representing the information comprises a number of digits, the number of digits equaling a number of parallel lines coupling the sender and the receiver. The digits of the selected symbol are sent from the sender to the receiver, wherein, via each of the number of lines, a signal representing one of the number of digits of the selected symbol is transferred. In the step of selecting a symbol, the symbol is selected such that the symbol differs from a lastly transferred symbol by one digit.
1. A method of transferring information from a sender to a receiver, the method comprising:
selecting a symbol out of a plurality of symbols representing the information, wherein each of the plurality of symbols representing the information comprises a number of digits, the number of digits equaling a number of parallel lines coupling the sender and the receiver; and
sending the digits of the selected symbol from the sender to the receiver, wherein, a signal representing one of the number of digits of the selected symbol is transferred via each of the number of lines,
wherein, in the step of selecting a symbol, the symbol is selected such that the symbol differs from a lastly transferred symbol by one digit.
2. The method of claim 1 , wherein each digit may take one of a predetermined plurality of predetermined values and wherein each value of each digit is represented by one of a predetermined plurality of levels of the signal.
3. The method of claim 2 , wherein the predetermined plurality of predetermined values of the digit comprises the values “0” and “1”, wherein a predetermined low level of a signal represents one of the predetermined plurality of predetermined values of the digit, and wherein a predetermined high level of the signal represents the other one of the predetermined plurality of predetermined values.
4. The method of claim 1 , wherein in the step of selecting a symbol, the symbol is always selected such that the parity of the symbol is different from a parity of the lastly transferred symbol if the information is different from the lastly transferred information.
5. The method of claim 3 , wherein in the step of selecting a symbol, the symbol is always selected such that the parity of the symbol is different from a parity of the lastly transferred symbol if the information is different from the lastly transferred information.
6. The method of claim 1 , wherein the sender is a memory controller, the receiver is a memory device, and the information is control information controlling the operation of the memory device.
7. The method of claim 1 , wherein the sender is a memory device, the receiver is a memory controller, and the information indicates an operational state of the memory device.
8. An integrated circuit with a sender, the sender comprising:
a number of outputs;
an output circuit coupled to the number of outputs and configured to transfer symbols via the number of outputs, wherein each symbol comprises a number of digits, the number of digits equaling the number of outputs, and the output circuit configured to transfer, via each of the number of outputs, a signal representing one of the number of digits; and
a symbol selection circuit configured to receive information and select a symbol out of a plurality of symbols representing the information, wherein the symbol selection circuit is configured to select the symbol such that the symbol differs from a lastly transferred symbol in one digit.
9. The integrated circuit of claim 8 , wherein each digit may take one of a predetermined plurality of predetermined values and wherein each value of each digit is represented by one of a predetermined plurality of levels of the signal.
10. The integrated circuit of claim 9 , wherein the predetermined plurality of predetermined values of the digit comprises the values “0” and “1”, wherein a predetermined low level of a signal represents one of the predetermined plurality of predetermined values of the digit, and wherein a predetermined high level of the signal represents the other one of the predetermined plurality of predetermined values.
11. The integrated circuit of claim 10 , wherein the symbol selection circuit selects a symbol such that a parity of the symbol is different from a parity of a lastly transferred symbol if the information are different from the previously transferred information.
12. The integrated circuit of claim 8 , wherein the sender is a memory controller and the information is control information controlling the operation of a memory device.
13. The integrated circuit of claim 8 , wherein the sender is a memory device, and the information indicates an operational state of the memory device.
14. An integrated circuit with a receiver, the receiver comprising:
a number of inputs;
a detection circuit coupled to the number of inputs and configured to receive symbols via the number of inputs, wherein each symbol comprises of a number of digits, the number of digits equaling the number of inputs, the detection circuit configured to receive, via each of the number of inputs, a signal representing one of the number of digits, and the detection circuit configured to detect an incoming symbol from a change of one signal at the number of inputs; and
a symbol identification circuit configured to receive, controlled by the detection circuit, the incoming symbol and identify information represented by the symbol when the detection circuit detects an incoming symbol.
15. The integrated circuit of claim 14 , wherein the detection circuit is configured to detect an incoming symbol from a change of a parity of the symbol.
16. The integrated circuit of claim 14 , wherein the detection circuit is configured to detect an incoming signal from a change of any signal at the number of input from one predetermined level out of a predetermined plurality of predetermined levels of the signal to another predetermined level out of the predetermined plurality of predetermined levels of the signal; and the symbol identification circuit identifying each digit of the symbol by identifying a predetermined level out of the predetermined plurality of predetermined levels at the corresponding line.
17. The integrated circuit of claim 16 , wherein each digit is either “0” or “1”, wherein each of a predetermined low level and a predetermined high level represents one of the values “0” and “1”.
18. The integrated circuit of claim 17 , wherein the detection circuit comprises:
a first XOR-gate, each of the number of inputs being coupled to a corresponding input of the first XOR-gate and each of the inputs of the first XOR-gate being coupled to one of the number of inputs.
19. The integrated circuit of claim 18 , wherein the detection circuit further comprises:
a second XOR-gate; and
a serial connection of an even number of inverters,
wherein an output of the first XOR-gate is coupled to a first input of the second XOR-gate, and wherein the output of the first XOR-gate is coupled to a second input of the second XOR-gate via the serial connection of inverters.
20. The integrated circuit of claim 19 , wherein the output of the first XOR-gate is directly coupled to the first input of the second XOR-gate.
21. The integrated circuit of claim 18 , wherein the detection circuit further comprises:
a second XOR-gate; and
a flip-flop,
wherein an output of the first XOR-gate is coupled to a first input of the second XOR-gate, wherein the output of the first XOR-gate is coupled to an input of the flip-flop, wherein an output of the flip-flop is coupled to a second input of the second XOR-gate, and wherein a clock input of the flip-flop is coupled to an output of the second XOR-gate.
22. The integrated circuit of claim 21 , wherein the output of the first XOR-gate is directly coupled to the first input of the second XOR-gate.
23. A system for transferring information, the system comprising a sender and a receiver;
the sender comprising:
a number of outputs;
an output circuit coupled to the number of outputs and configured to transfer symbols via the number of outputs, wherein each symbol comprises a number of digits, the number of digits equaling the number of outputs, and the output circuit configured to transfer, via each of the number of outputs, a signal representing one of the number of digits; and
a symbol selection circuit configured to receive information and select a symbol out of a plurality of symbols representing the information, the symbol selection circuit configured to select the symbol such that the symbol differs from a lastly transferred symbol in one digit, and
the receiver comprising:
a number of inputs;
a detection circuit coupled to the number of inputs and configured to receive symbols via the number of inputs, wherein each symbol comprises of a number of digits, the number of digits equaling the number of inputs, the detection circuit configured to receive, via each of the number of inputs, a signal representing one of the number of digits, and the detection circuit configured to detect an incoming symbol from a change of one signal at the number of inputs; and
a symbol identification circuit configured to receive, controlled by the detection circuit, the incoming symbol and identify information represented by the symbol when the detection circuit detects an incoming symbol.
24. The system of claim 23 , wherein the symbol selection circuit selects the symbol such that a parity of the symbol is different from a parity of the lastly transferred symbol if the information is different from the lastly transferred information.
25. The integrated circuit of claim 23 , the detection circuit further comprising:
a first XOR-gate, each of the number of inputs being coupled to a corresponding input of the first XOR-gate and each of the inputs of the first XOR-gate being coupled to one of the number of inputs.
26. The integrated circuit of claim 23 , the detection circuit further comprising:
a second XOR-gate; and
a serial connection of an even number of inverters,
wherein an output of the first XOR-gate is coupled to a first input of the second XOR-gate, and wherein the output of the first XOR-gate is coupled to a second input of the second XOR-gate via the serial connection of inverters.