Method and device for redundancy replacement in semiconductor devices using a multiplexer
View Patent ↗A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.
1. A method for replacing a faulty memory cell with a redundant memory cell in a memory array based on row groups and column select line segments, where the memory array contains a defective row with a faulty memory cell and a defective column select line segment with a faulty memory cell, the method comprising:
obtaining a row group physical address identifying the row group that includes a redundant row for replacing the defective row from a row group logical address identifying the row group that includes the defective row, the row group including the defective row being different than the row group including the redundant row,
remapping the defective row to the redundant row based on the row group logical address, and
remapping the defective column select line segment to a redundant column select line segment based on the row group physical address.
2. The method for repairing a faulty memory cell with a redundant memory cell according to claim 1 , wherein the remapping of the defective row includes comparing the row group logical address with stored addresses identifying faulty memory cells by a row group address.
3. The method for repairing a faulty memory cell with a redundant memory cell according to claim 1 , wherein the remapping of the defective column select line includes comparing the address of the defective column select line segment with stored addresses identifying faulty memory cells by a column select line segment address.
4. The method for repairing a faulty memory cell with a redundant memory cell according to claim 1 , wherein the remapping of the column select line segment includes a column depth of the memory array selected by a multiplexer.
5. The method for repairing a faulty memory cell with a redundant memory cell according to claim 1 , further comprising:
a row address latch receiving a memory address from an address bus;
a decoder receiving a row group address from the row address latch and supplying the row group logical address to a multiplexer;
a redundancy circuit receiving the memory address from the row address latch and supplying the row group physical address to the multiplexer;
the multiplexer selecting one of the row group logical or physical address based on redundancy and supplying a column select line segment address to the column select line repair circuit; and
the column select line repair circuit performing column select line segment repair based upon the column select line segment address received from the multiplexer.