System and method for signal adjustment
View Patent ↗Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal.
1. A method, comprising:
receiving a configuration selection of a delay-locked loop (“DLL”) component, the configuration selection setting a value of an initial delay of the DLL component;
inputting a delayed reference signal to a phase detector;
producing an output signal based on the configuration selection;
outputting the output signal to a feedback delay circuit;
receiving a feedback signal from the feedback delay circuit;
comparing the feedback signal to the delayed reference signal; and
adjusting the value of the initial delay of the DLL component until the feedback signal matches the delayed reference signal and locking the output signal of the DLL component, wherein the adjusting the value of the initial delay of the DLL component includes one of incrementing the value of the initial delay and decrementing the value of the initial delay.
2. The method of claim 1 , further comprising:
transmitting an adjusted output signal based on the adjusted value of the DLL component.
3. The method of claim 2 , further comprising:
initializing the DLL component into a normal operating mode prior to transmitting the adjusted output signal.
4. The method of claim 1 , further comprising:
storing in a memory, a predetermined initial minimum number of the value of the initial delay, wherein the predetermined initial minimum number is set in the memory based on one of a mode register set command, a fuse and an e-fuse.
5. The method of claim 1 , wherein the value of the initial delay corresponds to an adjustable initial minimum number of delay elements.
6. The method of claim 1 , further comprising:
initializing the DLL component into an initial mode prior to applying the delayed reference signal.
7. The method of claim 1 , wherein the adjusting the value of the initial delay is performed by one of a control circuit, a microprocessor, an application-specific integrated circuit, and an embedded controller.
8. A delay-locked loop (“DLL”) device, comprising:
a programmable fuse storing a value of an initial delay of the DLL device; and
a control circuit configured to operate in a seek mode and a locked mode,
wherein, while in seek mode, the control circuit:
receives a delayed reference signal to a phase detector;
receives a feedback signal from the feedback delay circuit;
compares the feedback signal to the delayed reference signal; and
adjusts the value of the initial delay to an adjusted value until the feedback signal matches the delayed reference signal, and
wherein, while in seek mode, the control circuit:
locks an output signal of the DLL device; and
instructs the DLL device to transmit an adjusted output signal based on the adjusted value of the DLL device.
9. The DLL device of claim 8 , wherein the adjusting the value of the initial delay of the DLL device includes one of incrementing the value of the initial delay and decrementing the value of the initial delay.
10. The DLL device of claim 8 , wherein the value of the initial delay corresponds to an adjustable initial minimum number of delay elements.
11. The DLL device of claim 8 , wherein the value of the initial delay stored in the memory may be set using one of a mode register set command, a fuse, and an electronically programmable fuse.
12. The DLL device of claim 8 , wherein the value of the initial delay corresponds to a cascading plurality of delay elements, each having a substantially fixed delay time.
13. The DLL device of claim 12 , wherein a signal output by one of the delay elements includes a delay corresponding to the fixed delay time of the one delay element and preceding cascaded delay elements.
14. A control circuit, comprising:
a counter selecting a value of an initial delay for a delay-locked loop;
a processor comparing a received output signal to a received feedback signal and determining whether one of a positive delay, a negative delay, and no delay is needed based on the comparing of the received output signal to the received feedback signal,
wherein the processor performs one of:
increasing the value selected in the counter when positive delay is needed,
decreasing the value selected in the counter when negative delay is needed, and
maintaining the value of the counter when no delay is needed.
15. The control circuit of claim 14 , wherein the processor transmits the output signal based on a maintained value of the counter.
16. The control circuit of claim 14 , wherein the processor transmits an adjusted output signal based on an adjusted value of the counter.
17. The control circuit of claim 14 , further comprising:
a memory storing the value of the initial delay for the delay-locked loop based on a user-specified DLL configuration.
18. The control circuit of claim 17 , wherein the output signal is generated by a phase detector of the delay-locked loop based on the user-specified DLL configuration.
19. The control circuit of claim 14 , wherein the value stored in the memory may be set using one of a mode register set command, a fuse, and an electronically programmable fuse.