Multiple write configurations for a memory cell
View Patent ↗The present invention relates to a method of programming an array of memory cells such as phase change memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, wherein the first and second pulse configurations are different, and wherein each pulse configuration can write at least two data states to the memory cells of the array.
1. A memory device, comprising:
an array of resistive memory cells;
control circuitry configured to provide first and second pulse configurations to write data to the resistive memory cells, the first pulse configuration comprising: a first reset pulse having a first peak current and a first quench time and a first set pulse having a first set pulse length; and the second pulse configuration comprising: a second reset pulse having a second peak current and a second quench time that is longer than the first quench time and a second set pulse having a second set pulse length that is less than the first set pulse length,
wherein a quench time of a reset pulse is defined as a time period associated with a falling edge of the reset pulse, and wherein both the first and second reset pulses result in a programmable volume of a respective resistive memory cell being in an amorphous state.
2. The memory device of claim 1 , where the resistive memory cells are phase-change memory cells and the first peak current is sufficient to remove crystallization nuclei from programmable volumes associated with the phase-change memory cells.
3. The memory device of claim 1 , where the quench time is adjusted by adjusting a gate voltage on a quench transistor of a bitline.
4. The memory device of claim 1 , where the quench time of the second reset pulse is sufficient to form some crystallization nuclei in programmable volumes associated with the phase-change memory cells.
5. The memory device of claim 1 , wherein the quench time of a reset pulse is defined as a time period a falling edge of the reset pulse takes to fall from a minimum current level associated with a melting point of a material associated with the resistive memory cells, and a maximum current level associated with a crystallization point of the material.
6. A memory device comprising:
means for storing bits of data;
means for providing first and second pulse configurations to write data to the means for storing the bits of data, the first pulse configuration comprising: a first reset pulse having a first quench time and a first set pulse having a first set pulse length; and the second pulse configuration comprising: a second reset pulse having a second quench time that is longer than the first quench time and a second set pulse having a second set pulse length that is less than the first set pulse length,
wherein a quench time of a reset pulse is defined as a time period associated with a falling edge of the reset pulse, and wherein both the first and second reset pulses result in a programmable volume of a respective resistive memory cell being in an amorphous state.
7. The memory device of claim 6 , wherein the quench time of a reset pulse is defined as a time period a falling edge of the reset pulse takes to fall from a minimum current level associated with a melting point of a material associated with the resistive memory cells, and a maximum current level associated with a crystallization point of the material.
8. A data processing system, comprising:
data processing circuitry; and
a memory associated with the data processing circuitry, the memory being accessible via first and second pulse configurations, the first pulse configuration comprising: a first reset pulse having a first quench time and a first set pulse having a first set pulse length; and the second pulse configuration comprising: a second reset pulse having a second quench time that is longer than the first quench time and a second set pulse having a second set pulse length that is less than the first set pulse length,
wherein a quench time of a reset pulse is defined as a time period associated with a falling edge of the reset pulse, and wherein both the first and second reset pulses result in a programmable volume of a respective resistive memory cell being in an amorphous state.
9. The data processing system of claim 8 , where the first reset pulse has a first peak current and second reset pulse has a second peak current that is less than the first peak current.
10. The data processing system of claim 8 , where the first reset pulse has a first falling edge slope and second reset pulse has a second falling edge slope that is more gradual than the first falling edge slope.
11. The data processing system of claim 8 , where the memory comprises an array of phase-change memory cells.
12. The data processing system of claim 8 , where the data processing system comprises a communication device, a portable electronic product, or an electronic system.
13. The data processing system of claim 8 , wherein the quench time of a reset pulse is defined as a time period a falling edge of the reset pulse takes to fall from a minimum current level associated with a melting point of a material associated with the resistive memory cells, and a maximum current level associated with a crystallization point of the material.