Circuit for programming a memory element

1. An integrated circuit comprising:

a memory element; and

a circuit configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance, the one or more pulses having a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance.

2. The integrated circuit of claim 1 , wherein the parameter value (PV) is modified for each subsequent pulse (n+1) by: PV(n+1)=PV(n)+[(log(sensed resistance)−log(desired resistance))*PV(n)*(a gain factor)], where n equals a pulse number for the immediately preceding pulse.

3. The integrated circuit of claim 2 , wherein the gain factor is a constant.

4. The integrated circuit of claim 2 , wherein the gain factor is based on the pulse number.

5. The integrated circuit of claim 1 , wherein the parameter value (PV) is modified for each subsequent pulse (n+1) by: PV(n+1)=10 {log(PV(n))+[(log(sensed resistance)−log(desired resistance))*log(PV(n))*(a gain factor)]} , where n equals a pulse number for the immediately preceding pulse.

6. The integrated circuit of claim 5 , wherein the gain factor is a constant.

7. The integrated circuit of claim 5 , wherein the gain factor is based on the pulse number.

8. The integrated circuit of claim 1 , wherein the parameter value for an initial pulse comprises a best guess for achieving the desired resistance.

9. The integrated circuit of claim 1 , wherein the parameter value comprises a pulse duration.

10. The integrated circuit of claim 1 , wherein the parameter value comprises a pulse amplitude.

11. The integrated circuit of claim 1 , wherein the parameter value comprises a pulse tail portion slope.

12. The integrated circuit of claim 1 , wherein the memory element is configured to be programmed to any one of at least three resistance states.

13. The integrated circuit of claim 1 , wherein the memory element comprises a phase change element.

14. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a memory element configured to be programmed to any one of at least three resistances; and

a circuit configured to program the memory element to a target resistance by:

applying a first pulse to the memory element, the first pulse including a first portion corresponding to the target resistance;

sensing a resistance of the memory element;

comparing the sensed resistance to the target resistance; and

applying a second pulse to the memory element in response to the comparison indicating that the sensed resistance is not within a range of the target resistance, the second pulse including a second portion that is modified from the first portion by a value proportional to a difference between the sensed resistance and the target resistance.

15. The system of claim 14 , wherein the second portion is modified from the first portion by a value proportional to a difference between a log of the sensed resistance and a log of the target resistance times a gain factor.

16. The system of claim 15 , wherein the gain factor is a constant.

17. The system of claim 15 , wherein the gain factor decreases for each pulse applied to the memory element.

18. The system of claim 14 , wherein one of a duration, an amplitude, and a slope of the second portion is modified from the first portion.

19. A memory comprising:

a multi-bit phase change element; and

means for programming the phase change element to a desired resistance by:

applying a first pulse to the phase change element, the first pulse including a first tail portion corresponding to the desired resistance;

determining a resistance of the phase change element;

comparing the determined resistance to the desired resistance; and

applying a second pulse to the phase change element in response to the comparison indicating that the determined resistance is not within a range of the desired resistance, the second pulse including a second tail portion that is modified from the first tail portion by a value proportional to a difference between a log of the determined resistance and a log of the desired resistance.

20. The memory of claim 19 , wherein applying the second pulse comprises applying the second pulse in response to the comparison indicating that the determined resistance is not within a range of +/−5% on a linear or log scale of the desired resistance.

21. A method for programming a memory element, the method comprising:

applying one or more pulses to a memory element until a sensed resistance of the memory element is within a range of a desired resistance, the one or more pulses having a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance.

22. The method of claim 21 , wherein the parameter value (PV) is modified for each subsequent pulse (n+1) by: PV(n+1)=PV(n)+[(log(sensed resistance)−log(desired resistance))*PV(n)*(a gain factor)], where n equals a pulse number for the immediately preceding pulse.

23. The method of claim 22 , further comprising:

setting the gain factor to a constant.

24. The method of claim 22 , further comprising:

setting the gain factor based on the pulse number.

25. The method of claim 21 , wherein the parameter value (PV) is modified for each subsequent pulse (n+1) by: PV(n+1)=10 {log(PV(n))+[(log(sensed resistance)−log(desired resistance))*log(PV(n))*(a gain factor)]} , where n equals a pulse number for the immediately preceding pulse.

26. The method of claim 25 , further comprising:

setting the gain factor to a constant.

27. The method of claim 25 , further comprising:

setting the gain factor based on the pulse number.

28. The method of claim 21 , further comprising:

setting the parameter value for an initial pulse to a best guess value for achieving the desired resistance.

29. The method of claim 21 , wherein applying the one or more pulses comprises applying the one or more pulses having a parameter value comprising one of a pulse duration, a pulse amplitude, and a pulse tail portion slope that is modified for each subsequent pulse.

30. The method of claim 21 , wherein applying the one or more pulses comprises applying the one or more pulses to a memory element configured to be programmed to any one of at least three resistance states.

31. The method of claim 21 , wherein applying the one or more pulses to the memory element comprises applying the one or more pulses to a phase change element.

32. A method for programming a phase change element, the method comprising:

applying a first pulse to a phase change element, the first pulse including a first portion corresponding to a target resistance,

sensing a resistance of the phase change element;

comparing the sensed resistance to the target resistance; and

applying a second pulse to the phase change element in response to the comparison indicating that the sensed resistance is not within a range of the target resistance, the second pulse including a second portion that is modified from the first portion by a value proportional to a difference between a log of the sensed resistance and a log of the target resistance.

33. The method of claim 32 , wherein applying the second pulse comprises applying the second pulse including a second portion that has a modified duration from the first portion.

34. The method of claim 32 , wherein applying the second pulse comprises applying the second pulse including a second portion that has a modified amplitude from the first portion.

35. The method of claim 32 , wherein applying the second pulse comprises applying the second pulse including a second portion that has a modified slope from the first portion.