Semiconductor memory having a bank with sub-banks

1. A hierarchical-bank memory, comprising:

a plurality of input address pins; and

a plurality of banks, wherein each of the plurality of banks comprises:

a plurality of sub-banks, wherein a selection of a sub-bank is determined by the plurality of input address pins and wherein a minimum allowable time interval between successive commands to different sub-banks of the same bank (tRCsub) is shorter than a minimum allowable time interval between successive commands to the same sub-bank (tRC) of the same bank.

2. The memory of claim 1 , wherein one or more pins of the plurality of input address pins are provided to selectively address the plurality of sub-banks of the hierarchical-bank memory.

3. The memory of claim 1 , wherein tRCsub is shorter than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

4. The memory of claim 1 , wherein tRCsub is longer than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

5. A hierarchical-bank memory, comprising:

a plurality of banks of memory cells, wherein each bank comprising a plurality of separately addressable sub-banks;

a sub-bank interface for each of the separately addressable sub-banks, wherein activation of a sub-bank interface is determined by a plurality of address pins; and

a row decoder for each of the separately addressable sub-banks configured to activate a word line of a respective sub-bank in response to one or more control signals and one or more address signals received from a respective sub-bank interface, wherein a minimum allowable time interval between successive commands to different sub-banks of the same bank (tRCsub) is shorter than a minimum allowable time interval between successive commands to the same sub-bank (tRC) of the same bank.

6. The memory of claim 5 , wherein one or more pins of the plurality of address pins are provided to selectively address the plurality of separately addressable sub-banks of the hierarchical-bank memory.

7. The memory of claim 5 , wherein the hierarchical bank memory further comprises a column decoder configured to access a column of any of the plurality of separately addressable sub-banks, and wherein the column decoder is activated in response to one or more control signals and one or more address signals received by a sub-bank interface.

8. The memory of claim 5 , wherein the separately addressable sub-banks share a common data path.

9. The memory of claim 7 , wherein a first sub-bank interface is configured to control the column decoder to initiate a first column access, and wherein a second sub-bank interface is configured to control the column decoder to initiate a second column access after tRCsub for the first column access elapses.

10. The memory of claim 5 , wherein tRCsub is shorter than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

11. The memory of claim 5 , wherein tRCsub is longer than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

12. A method for accessing a hierarchical bank memory, wherein the hierarchical bank memory comprises a plurality of sub-banks, comprising:

receiving a command from a controller via a control bus;

receiving an address associated with the command from the controller via one or more address buses;

configuring a plurality of sub-bank interfaces located in the hierarchical bank memory to select a respective row decoder located in the hierarchical bank memory in response to the address, wherein a number of sub-bank interfaces and respective row decoders is equal to a number of sub-banks within the hierarchical bank memory; and

activating the respective row decoder located in the hierarchical bank memory in response to one or more control signals and one or more address signals, received from a respective sub-bank interface, thereby activating a word line of a respective sub-bank, wherein activation of a sub-bank interface is determined by the address received via the one or more address buses and wherein a minimum allowable time interval between successive commands to different sub-banks of a same bank (tRCsub) is shorter than a minimum allowable time interval between successive commands to the same sub-bank (tRC) of the same bank.

13. The method of claim 12 , wherein each of the one or more address buses bus is configured to access a different hierarchy of the hierarchical-bank memory.

14. The method of claim 12 , wherein the method further comprises the step of:

configuring a column decoder located in the hierarchical bank memory to access a column of any of the plurality of sub-banks, and wherein the column decoder is activated in response to one or more control signals and one or more address signals received by a sub-bank interface.

15. The method of claim 14 , wherein the method further comprises the steps of:

configuring a first sub-bank interface to control the column decoder to initiate a first column access; and

configuring a second sub-bank interface to control the column decoder to initiate a second column access after tRCsub for the first column access elapses.

16. The method of claim 12 , wherein tRCsub is shorter than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

17. The method of claim 12 , wherein tRCsub is longer than a minimum allowable time interval between successive commands to different banks of the hierarchical-bank memory (tRRD).

18. A system, comprising:

a controller; and

at least one memory device communicatively coupled to the controller, comprising:

a plurality of banks of memory cells, each bank comprising a plurality of separately addressable sub-banks;

a sub-bank interface for each of the separately addressable sub-banks; and

a row decoder for each of the separately addressable sub-banks configured to activate a word line of a respective sub-bank in response to one or more control signals and one or more address signals received from a respective sub-bank interface; wherein a selection of a sub-bank interface is determined by a plurality of address pins and wherein a minimum allowable time interval between successive commands to different sub-banks of the same bank (tRCsub) is shorter than a minimum allowable time interval between successive commands to the same sub-bank (tRC) of the same bank.

19. The system of claim 18 , wherein the plurality of address pins are coupled between the controller and the memory device, and wherein one or more pins of the plurality of address pins are provided to selectively address the plurality of separately addressable sub-banks of the memory device.

20. The system of claim 18 , wherein the memory device further comprises a column decoder configured to access a column of any of the plurality of separately addressable sub-banks, and wherein the column decoder is activated in response to one or more control signals and one or more address signals received by a sub-bank interface.

21. The system of claim 18 , wherein the separately addressable sub-banks share a common data path.

22. The system of claim 20 , wherein a first sub-bank interface is configured to control the column decoder to activate a first column access, and a second sub-bank interface is configured to control the column decoder to initiate a second column access after tRCsub for the first column access elapses.

23. The system of claim 18 , wherein tRCsub is shorter than a minimum allowable time interval between successive commands to different banks of the memory device (tRRD).

24. The system of claim 18 , wherein tRCsub is longer than a minimum allowable time interval between successive commands to different banks of the memory device (tRRD).