Patent Assignment
Reel/Frame 036575/0670
Assignment of Assignor's Interest
Recorded: 2015-09-09
Pages: 8
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(121)
Multi-Chip Module
Sense-Amplifier Circuit for a Memory Device with an Open Bit Line Architecture
Sense Amplifier Biasing Method and Apparatus
Memory Cell Array Comprising Floating Body Memory Cells
Integrated Circuit
Memory Circuit
Method and Apparatus for Determining a Skew
Apparatus and Method for Generating a Transmit Signal and Apparatus and Method for Extracting an Original Message from a Received Signal
Integrated Circuit Including Memory Having Reduced Cross Talk
Memory System with Extended Memory Density Capability
Assembly Device and Assembly Method for a Cooling Element
Command Protocol for Integrated Circuits
Integrated Circuit for Setting a Memory Cell Based on a Reset Current Distribution
Multi-Die Memory, Apparatus and Multi-Die Memory Stack
Semiconductor Packaging Device
Method and Apparatus for Storage Device with a Logic Unit and Method for Manufacturing Same
Manufacturing Method for Forming an Integrated Circuit Device and Corresponding Integrated Circuit Device
Electrode of an Integrated Circuit
Integrated Circuit, and Method for Transferring Data
Semiconductor Memory Having a Bank with Sub-Banks
Controlling an Analog Signal in an Integrated Circuit
Method of Making Transistor Gates with Controlled Work Function
Delay Locked Loop
Integrated Circuit and Method
Integrated Circuit Including U-Shaped Access Device
Integrated Circuit Including U-Shaped Access Device
Integrated Circuit Fabricated Using an Oxidized Polysilicon Mask
Integrated Circuit Including an Electrode Having an Outer Portion with Greater Resistivity
Apparatus and Method for Determining a Memory State of a Resistive N-Level Memory Cell and Memory Device
Methods and Articles of Manufacture for Operating Electronic Devices on a Plurality of Clock Signals
Methods and Apparatus for Operating a Digital Communications Interface
Memory That Retains Data When Switching Partial Array Self Refresh Settings
Termination Switching Based on Data Rate
Derivative Logical Output
Multi-Bank Memory Device Method and Apparatus
Integrated Circuit Including Memory Refreshed Based on Temperature
Memory Including Periphery Circuitry to Support a Portion or All of the Multiple Banks of Memory Cells
Systems and Methods of Alternative Overlay Calculation
Method and Device for Generating a Digital Data Signal and Use Thereof
Semiconductor Device with an Interconnect Element and Method for Manufacture
Semiconductor Chip with Integrated Via
Integrated Circuit and Method of Fabricating the Same
Integrated Circuit Including a Body Transistor and Method
Integrated Circuit with Wireless Connection
Interface Voltage Adjustment Based on Error Detection
Measurement Method for Determining Dimensions of Features Resulting from Enhanced Patterning Methods
System and Method of Correcting Errors in Sem-Measurements
Semiconductor Component with Improved Contact Pad and Method for Forming the Same
Integrated Circuit with an Array of Resistance Changing Memory Cells
Semiconductor Device
Integrated Circuit Including an Insulating Structure Below a Source/Drain Region and Method
Integrated Circuit with Conductive Structures
Semiconductor Component with Mim Capacitor
Storage Cell Having a T-Shaped Gate Electrode and Method for Manufacturing the Same
Integrated Circuit That Stores First and Second Defective Memory Cell Addresses
Integrated Circuit That Stores Defective Memory Cell Addresses
Word Line to Bit Line Spacing Method and Apparatus
Integrated Circuit Including a Buried Wiring Line
Integrated Circuit Including an Array of Diodes Coupled to a Layer of Resistance Changing Material
Integrated Circuit Including a Memory Element Programmed Using a Seed Pulse
Isolation Trenches with Conductive Plates
Method and Apparatus for Selectively Disabling Termination Circuitry
Integrated Circuits Having a Contact Structure Having an Elongate Structure and Methods for Manufacturing the Same
Integrated Circuit Having a Magnetic Tunnel Junction Device and Method
Magnetoresistive Sensor with Tunnel Barrier and Method
Integrated Circuits, Standard Cells, and Methods for Generating a Layout of an Integrated Circuit
Integrated Circuit Including Memory Element with Spatially Stable Material
Integrated Circuit Including a Dielectric Layer
Integrated Circuit Including a Vertical Transistor and Method
Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit
Method for Manufacturing a Multichip Module Assembly
Fb Dram Memory with State Memory
Field Effect Transistors with Channels Oriented to Different Crystal Planes
Alignment Calculation
Bus Termination System and Method
Integrated Circuit Including Selectable Address and Data Multiplexing Mode
Integrated Circuit with Bit Lines Positioned in Different Planes
Circuit with Selectable Data Paths
Patent:
7,646,320 →
Application:
12/193,698 →
High Speed Memory Architecture
Integrated Circuit and Programmable Delay
Integrated Circuit Including Memory Cell Having Cup-Shaped Electrode Interface
Electronic Device Having a Chip Stack
Memory Device with Multiple Capacitor Types
Digital Data Inversion Flag Generator Circuit
Multi-Mode Bus Inversion Method and Apparatus
Integrated Circuit Including Doped Semiconductor Line Having Conductive Cladding
Phase Change Memory Cell with Mosfet Driven Bipolar Access Device
Horizontal Dual in-Line Memory Modules
System and Method for Packaged Memory
Memory Dies for Flexible Use and Method for Configuring Memory Dies
Method and System Including Plural Memory Controllers and a Memory Access Control Bus for Accessing a Memory Device
Multi-Port Dram Architecture for Accessing Different Memory Partitions
Memory Device Refresh Method and Apparatus
Integrated Circuit with a Rectifier Element
Method of Manufacturing Integrated Circuits Including a Fet with a Gate Spacer and a Fin
Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same
Integrated Circuit
Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling
Memory Device and Memory System Comprising a Memory Device and a Memory Control Device
Interconnect Structure for Semiconductor Devices
Integrated Circuit with Control Circuit for Performing Retention Test
Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure
Interconnect Structures and Methods
Packaging Systems and Methods
4 F2 Memory Cell Array
Memory Cell Array Comprising Wiggled Bit Lines
Integrated Circuit with Stacked Devices
Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface
Digitally Controlled Cml Buffer
Distributed Command and Address Bus Architecture for a Memory Module Having Portions of Bus Lines Separately Disposed
Integrated Circuit, Method to Program a Memory Cell Array of an Integrated Circuit, and Memory Module
Chip Arrangement and Method of Manufacturing a Chip Arrangement
Photovoltaic Device
Resistive Memory Cell Accessed Using Two Bit Lines
Semiconductor Memory Having Non-Standard Form Factor
Semiconductor Memory with Memory Cell Portions Having Different Access Speeds
Memory Device Including an Electrode Having an Outer Portion with Greater Resistivity
Integrated Circuit and Programmable Delay
Memory Devices Including Semiconductor Pillars
Semiconductor Memory Having Non-Standard Form Factor
Integrated Circuits, Standard Cells, and Methods for Generating a Layout of an Integrated Circuit
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.