Semiconductor memory having non-standard form factor

1. A semiconductor memory chip comprising:

error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits; and

at least one memory cell array configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

2. The memory chip of claim 1 , wherein the memory chip comprises a DRAM memory and the memory cell array comprises 8f2-type memory cells.

3. The memory chip of claim 1 , wherein the code words comprise a non-binary number of bits of which is a factor of three.

4. The memory chip of claim 1 , wherein the error correction circuitry employs a minimum odd weight code scheme to encode 64 data bits as a 74-bit coded word.

5. The memory chip of claim 1 , wherein the error correction circuitry employs a 12/8 Hamming code scheme to encode 64 data bits as eight, 12-bit coded words.

6. A semiconductor memory chip comprising:

error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits; and

at least one memory cell array configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio, wherein the error correction circuitry employs a minimum odd weight code scheme to encode 64 data bits as a 74-bit coded word, and wherein the at least one memory cell array comprises four memory cell array blocks, each block having an effective density of 288 Mbits with the four memory cell array blocks together providing an effective density of 1152 Mbits and a data storage density of 1024 Mbits, and wherein the four memory cell array blocks are arranged so as to provide the memory chip with a form factor having substantially a 1:1 aspect ratio.

7. A semiconductor memory chip comprising:

error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits; and

at least one memory cell array configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio, wherein the error correction circuitry employs a 12/8 Hamming code scheme to encode 64 data bits as eight, 12-bit coded words, and wherein the at least one memory cell array comprises four memory cell array blocks, each block having an effective density of 96 Mbits with the four memory cell array blocks together providing an effective density of 384 Mbits and a data storage density of 256 Mbits, and wherein the four memory cell array blocks are arranged so as to provide the memory chip with a form factor having substantially a 1:1 aspect ratio.