Integrated circuit including a memory element programmed using a seed pulse

1. An integrated circuit comprising:

a phase change element; and

a circuit configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the phase change element followed by a set pulse,

wherein the seed pulse reduces a volume of amorphous phase change material within the phase change element while increasing a density of nucleation sites within the amorphous phase change material.

2. The integrated circuit of claim 1 , wherein the seed pulse comprises a borderline reset pulse.

3. The integrated circuit of claim 1 , wherein the set pulse comprises one of a multi-step set pulse and a ramping tail set pulse.

4. The integrated circuit of claim 1 , wherein the circuit is configured to provide a delay between the seed pulse and the set pulse.

5. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a phase change element; and

a write circuit configured to program the phase change element to a crystalline state from an amorphous state by:

reducing a volume of amorphous phase change material within the phase change element while increasing a density of nucleation sites within the amorphous phase change material; and

transitioning the reduced volume of amorphous phase change material to the crystalline state.

6. The system of claim 5 , wherein the write circuit is configured to program the phase change element to the crystalline state from the amorphous state by applying a seed pulse followed by a set pulse to the phase change element.

7. The system of claim 5 , wherein the write circuit is configured to program the phase change element to the crystalline state from the amorphous state by applying a seed-set pulse to the phase change element.

8. A method for operating a memory, the method comprising:

programming a resistance changing memory element to a crystalline state from an amorphous state, the programming comprising:

applying a seed pulse to the memory element; and

applying a set pulse to the memory element following the seed pulse;

wherein programming the resistance changing memory element comprises programming a phase change element, and

wherein applying the seed pulse comprises applying the seed pulse to increase a density of nucleation sites within amorphous phase change material within the memory element.

9. The method of claim 8 , wherein applying the seed pulse comprises applying a borderline reset pulse.

10. The method of claim 8 , wherein applying the seed pulse comprises applying the seed pulse to reduce a volume of amorphous phase change material within the memory element.

11. The method of claim 8 , wherein applying the set pulse comprises applying one of a multi-step set pulse and a ramping tail set pulse.

12. The method of claim 8 , further comprising:

delaying a set time after the seed pulse before applying the set pulse.

13. A method for operating a memory, the method comprising:

programming a phase change element to a crystalline state from an amorphous state, the programming comprising:

reducing a volume of amorphous phase change material within the phase change element while increasing a density of nucleation sites within the amorphous phase change material; and

transitioning the reduced volume of amorphous phase change material to the crystalline state,

wherein transitioning the reduced volume of amorphous phase change material to the crystalline state comprises heating the reduced volume of amorphous phase change material above its crystallization temperature.

14. The method of claim 13 , wherein reducing the volume of amorphous phase change material within the phase change element while increasing the density of nucleation sites within the amorphous phase change material comprises heating a portion of the amorphous phase change material to near melting.

15. An integrated circuit comprising:

a phase change memory element; and

a circuit configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse,

wherein the memory element in the amorphous state comprises a volume of amorphous phase change material with nucleation sites within the volume of amorphous phase change material, and

wherein the seed pulse reduces the volume of amorphous phase change material within the memory element while increasing a density of the nucleation sites within the volume of amorphous phase change material.

16. The integrated circuit of claim 15 , wherein the circuit is configured to provide a delay between the seed pulse and the set pulse.