IP Library Granted Patent US 7,872,350
Granted Patent B2
US 7,872,350 · App. 11/733,679 · Granted Jan 18, 2011

Multi-chip module

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Quick Facts
Patent No.
US 7,872,350
App. No.
11/733,679
Granted
Jan 18, 2011
Kind
B2
Abstract

A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.

Claims (21)

1. A multi-chip module, comprising:

at least one integrated circuit chip that is electrically coupled externally only to first external terminals of the multi-chip module wherein all first external terminals of the multi-chip module define a first contiguous region of a terminal area of the multi-chip module; and

at least one power semiconductor chip that is electrically coupled externally only to second external terminals of the multi-chip module, wherein all of the second external terminals of the multi-chip module are arranged in a second contiguous region of the terminal area separate from the first contiguous region, wherein the terminal area of the multi-chip module is a bottom of the multi-chip module, and wherein one of the first and second external terminals are disposed along all four sides of the bottom of the multi-chip module.

2. The multi-chip module according to claim 1 , wherein the integrated circuit chip is a standard power integrated circuit.

3. The multi-chip module according to claim 1 , wherein the first contiguous region is defined by one linear array or a plurality of adjoining linear arrays of first external terminals.

4. The multi-chip module according to claim 1 , wherein the first contiguous region is defined by a two-dimensional array of first external terminals.

5. The multi-chip module according to claim 1 , wherein at least one side of the terminal area along which second external terminals extend is free of first external terminals.

6. The multi-chip module according to claim 1 , wherein the at least one integrated circuit chip and the at least one power semiconductor chip are arranged at opposite sides of the multi-chip module.

7. The multi-chip module according to claim 1 , wherein the at least one integrated circuit comprises a logic circuit.

8. The multi-chip module according to claim 1 , wherein the at least one integrated circuit comprises a control circuit for controlling the at least one power semiconductor chip.

9. The multi-chip module according to claim 1 , wherein the multi-chip module comprises part of a voltage converter circuitry.

10. A multi-chip module, comprising:

at least one integrated circuit chip that is electrically coupled externally only to first external terminals of the multi-chip module wherein all first external terminals of the multi-chip module define a first contiguous region of a terminal area of the multi-chip module; and

at least one power semiconductor chip that is electrically coupled externally only to second external terminals of the multi-chip module, wherein all second external terminals of the multi-chip module are arranged in a second contiguous region of the terminal area separate from the first contiguous region, and wherein the first contiguous region and the second contiguous region are separated over the terminal area by an O-shaped line or a closed polygonal line.

11. The multi-chip module according to claim 1 , wherein the first contiguous region is located at about the center of the terminal area.

12. The multi-chip module according to claim 1 , further comprising a chip carrier on which the at least one integrated circuit chip is mounted.

13. The multi-chip module according to claim 1 , wherein the at least one power semiconductor chip is mounted on a second external terminal.

14. The multi-chip module according to claim 1 , further comprising a mold compound encapsulating the at least one integrated circuit chip and the at least one power semiconductor chip.

15. The multi-chip module according to claim 10 , wherein the first contiguous region is located at about the center of the terminal area.

16. The multi-chip module according to claim 12 , wherein the chip carrier comprises a metal leadframe.

17. The multi-chip module according to claim 12 , wherein the chip carrier comprises insular pre-structured metal pads.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036575/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2008
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 021262/0590 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2007
From: OTREMBA, RALF; HOEGLAUER, JOSEF; LANDAU, STEFAN; HUBER, ERWIN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019495/0542 →