Chip arrangement and method of manufacturing a chip arrangement
View Patent ↗A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side.
1. A chip arrangement comprising:
a logic chip with electric contacts arranged on one side;
a memory chip arrangement with electrical contacts arranged on at least one side; and
a substrate with electrical contacts on opposite sides of the substrate, the substrate further including electrical connections between the electrical contacts on opposite sides,
wherein the logic chip is attached to the substrate and electrically conductively coupled to the substrate, and
wherein the memory chip arrangement is arranged on the logic chip on a side facing the substrate and is electrically conductively coupled to the logic chip, and
wherein the memory chip arrangement includes memory chips and at least one logic chip and, wherein the electrical connections between the electrical contacts of the memory chip arrangement and contacts of the memory chips and/or contacts between the memory chips and the at least one logic chip are formed as thru vias through the memory chips.
2. The chip arrangement according to claim 1 , wherein the memory chip arrangement is disposed above the substrate, wherein the logic chip is electrically conductively coupled to the substrate through solder contacts, and wherein the memory chip arrangement is disposed between the solder contacts.
3. The chip arrangement according to claim 1 , wherein a contact portion of the logic chip is larger than a contact portion of the memory chip arrangement.
4. The chip arrangement according to claim 1 , wherein the memory chip arrangement is located in a recess in the substrate.
5. The chip arrangement according to claim 4 , wherein the electrical contacts are arranged on the substrate around the recess.
6. The chip arrangement according to claim 4 , wherein the recess in the substrate comprises a bottom plane with contacts configured to electrically conductively connect to the electrical contacts of the memory chip arrangement facing the bottom plane.
7. The chip arrangement according to claim 4 , wherein the recess in the substrate is a thru hole.
8. The chip arrangement according to claim 1 , wherein the electrical connections of the substrate comprise thru vias through the substrate.
9. The chip arrangement according to claim 1 , wherein connections between contacts arranged on one side of the substrate are formed by a redistribution layer.
10. The chip arrangement according to claim 1 , wherein electrical contacts of the memory chip arrangement are connected to the electrical contacts of the substrate by a redistribution layer formed on the logic chip.
11. The chip arrangement according to claim 1 , further comprising an additional mounting layer with contacts, wherein the contacts are connected to the substrate on a side opposite to the logic chip.
12. The chip arrangement according to claim 11 , wherein the additional mounting layer is formed by a further substrate comprising at its bottom side and its upper side contacts for an electrically conductive connection.
13. The chip arrangement according to claim 12 , wherein electrical contacts of the memory chip arrangement are connected to the electric contacts of the logic chip on a side facing the logic chip and the electrical contacts of the memory chip arrangement are connected to the further substrate on a side opposite to the logic chip.