Apparatus and method for generating a transmit signal and apparatus and method for extracting an original message from a received signal

1. An apparatus for generating a transmit signal comprising data bits, the apparatus comprising:

a circuit for providing an indicator indicating whether the data bits represent an original message or an inverted version thereof;

a processor for determining check information that depends on the data bits and the indicator; and

a circuit for forming the transmit signal including the data bits, the indicator and at least a part of the check information.

2. The apparatus according to claim 1 , wherein the processor is further configured to determine a first check information assuming a first state of the indicator and to modify the first check information using a second check information if an actual state of the indicator is different from the first state.

3. The apparatus according to claim 2 , wherein the processor is further configured to determine the first check information temporally in parallel to providing the indicator.

4. The apparatus according to claim 2 , wherein the processor is further configured to modify the first check information based on a modulo-2 addition of the first check information and the second check information.

5. The apparatus according to claim 2 , wherein the first and second check information comprise a first checksum and a second checksum, each checksum comprising error-correcting bits.

6. The apparatus according to claim 5 , wherein the processor is further configured to determine the first checksum by extending the original message by at least one bit value indicating no inversion to obtain an extended original message, and by multiplying the extended original signal message by a code generator matrix.

7. The apparatus according to claim 5 , wherein the processor is further configured to form the second checksum by multiplying an all-ones-vector, having a length at least equal to a word length of the original message plus one, by a code generator matrix.

8. The apparatus according to claim 5 , wherein each check information is a checksum and wherein the processor is configured to determine the checksum based on

c=c 1 ⊕c 2 ·b,

wherein c is the checksum, c 1 denotes the first checksum, c 2 denotes the second checksum, b denotes the indicator and ⊕ denotes a modulo-2 addition.

9. The apparatus according to claim 1 , wherein the check information is a checksum, wherein the apparatus is capable of being coupled to a plurality of channels via which the data bits of the transmit signal are to be transmitted simultaneously in parallel, wherein the circuit for providing an indicator is configured to provide a first indicator for a first portion of the data bits and to provide a second indicator for a second portion of the data bits, and wherein the processor is configured to determine the checksum based on the data bits and the first and second indicators.

10. The apparatus according to claim 1 , wherein the check information is a checksum, wherein the apparatus is capable of being coupled to a plurality of channels via which the data bits of the transmit signal are to be transmitted simultaneously in parallel, wherein the processor is configured to determine the checksum based on the data bits, the indicator, additional data bits and an additional indicator indicating whether the additional data bits represent an original additional message or an inverted version thereof, wherein the additional data bits and the additional indicator are part of an additional transmit signal to be transmitted via the plurality of channels prior to or after the transmit signal, and wherein the circuit for forming the transmit signal is configured to form the transmit signal including a first portion of the checksum and to form the additional transmit signal including a second portion of the checksum.

11. The apparatus according to claim 1 , wherein the check information is a parity bit, wherein the processor is configured to determine the parity bit using the data bits and a checksum, the checksum depending on the data bits and the indicator.

12. An apparatus for extracting an original message from a received signal carrying information on data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and a check information which depends on the data bits and the indicator, the apparatus being comprising:

a processor for determining a check information based on the received data bits and a received indicator;

a circuit for comparing the determined check information with received check information; and

a circuit for extracting the original message based on the result of the comparison.

13. The apparatus according to claim 12 , wherein the processor is further configured to multiply at least received data bits and the received indicator with a parity-check matrix to determine the check information.

14. An apparatus for generating a transmit signal comprising data bits, the apparatus comprising:

a circuit for providing an indicator indicating whether the data bits represent an original message or an inverted version thereof;

a processor for determining a check information, wherein the check information is equal to a first check information when the indicator indicates that the data bits represent the original message and the check information is equal to the first check information modified by a second check information when in case the indicator indicates that the data bits represent the inverted version of the original message; and

a circuit for forming the transmit signal including the data bits, the indicator and the check information.

15. The apparatus according to claim 14 , wherein the processor is further configured to determine the first check information temporally in parallel to providing the indicator.

16. The apparatus according to claim 14 , wherein the processor is further configured to modify the first check information based on a modulo-2 addition of the first check information and the second check information.

17. The apparatus according to claim 14 , wherein the first and second check information comprise a first checksum and a second checksum, each checksum comprising error-correcting bits.

18. The apparatus according to claim 17 , wherein the processor is further configured to determine the first checksum by extending the original message by at least one bit value indicating no inversion to obtain an extended original message, and by multiplying the extended original signal message by a code generator matrix.

19. The apparatus according to claim 17 , wherein the processor is further configured to form the second checksum by multiplying an all-ones-vector, having a length at least equal to a word length of the original message plus one, by a code generator matrix.

20. The apparatus according to claim 17 , wherein the check information is a checksum and wherein the apparatus processor is configured to determine the checksum based on

c=c 1 ⊕c 2 ·b,

wherein c is the checksum, c 1 denotes the first checksum, c 2 denotes the second checksum, b denotes the indicator and ⊕ denotes a modulo-2 addition.

21. The apparatus according to claim 14 , wherein the check information is a checksum, wherein the apparatus is capable of being coupled to a plurality of channels via which the data bits of the transmit signal are to be transmitted simultaneously in parallel, wherein the circuit for providing an indicator is configured to provide a first indicator for a first portion of the data bits and to provide a second indicator for a second portion of the data bits, and wherein the processor is configured to determine the checksum based on the data bits and the first and second indicators.

22. The apparatus according to claim 14 , wherein the check information is a checksum, wherein the apparatus is capable of being coupled to a plurality of channels via which the data bits of the transmit signal are to be transmitted simultaneously in parallel, wherein the processor is configured to determine the checksum based on the data bits, the indicator, additional data bits and an additional indicator indicating whether the additional data bits represent an original additional message or an inverted version thereof, wherein the additional data bits and the additional indicator are part of an additional transmit signal to be transmitted via the plurality of channels prior to or after the transmit signal, and wherein the circuit for forming the transmit signal is configured to form the transmit signal including a first portion of the checksum and to form the additional transmit signal including a second portion of the checksum.

23. The apparatus according to claim 14 , wherein the check information is a parity bit, wherein the processor is configured to determine the parity bit using the data bits and a checksum, the checksum depending on the data bits and the indicator.

24. A method for generating a transmit signal comprising data bits, the method comprising:

providing an indicator indicating whether the data bits represent an original message or an inverted version thereof;

determining check information which depends on the data bits and the indicator; and

forming the transmit signal including the data bits, the indicator and at least a part of the check information.

25. A method for extracting an original message from a received signal comprising data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and a check information which depends on the data bits and the indicator, the method comprising:

determining a check information based on the received data bits and the received indicator;

comparing the determined check information with the received check information; and

extracting the original message based on the result of the comparison.