Integrated circuit including a dielectric layer

1. An integrated circuit comprising:

a substrate having a first side and a second side; and

at least one dielectric layer, the dielectric layer comprising a zirconium oxide and at least one dopant selected from the group comprising hafnium and titanium and having a first side and a second side, wherein the first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate,

wherein the dielectric layer comprises at least a region which is in any of a tetragonal, a cubic and an orthorhombic phase.

2. The integrated circuit of claim 1 , wherein the dielectric layer includes at least one dopant selected from the group comprising silicon or aluminum.

3. The integrated circuit of claim 1 , wherein a cap layer is provided, the cap layer having a first side and a second side and the first side of the cap layer being arranged on the second side of the dielectric layer.

4. The integrated circuit of claim 3 , wherein the cap layer comprises any of a silicon oxide and an aluminum oxide and a zirconium oxide.

5. The integrated circuit of claim 3 , comprising wherein any of the dielectric layer and the cap layer comprises a plurality of sublayers.

6. The integrated circuit of claim 5 , wherein any sublayer out of the plurality of sublayers comprises the same base material and a different dopant.

7. The integrated circuit of claim 1 , wherein the dielectric layer is in an antiferroelectric state.

8. The integrated circuit of claim 1 , comprising wherein the concentration of the dopants is in a range from 0.1%, up to 50%.

9. The integrated circuit of claim 1 , comprising wherein the dielectric layer is part of a transistor or a capacitor.

10. The integrated circuit of claim 9 , comprising wherein the transistor or the capacitor is part of a dynamic random access memory cell.

11. An integrated circuit comprising:

a substrate;

a cap layer;

at least one dielectric layer between the substrate assembly and the cap layer, the dielectric layer comprising:

a zirconium oxide and at least one dopant selected from the group comprising hafnium and titanium and having a first side and a second side, wherein the first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate,

wherein the dielectric layer is in an antiferroelectric state.

12. The integrated circuit of claim 11 , wherein the cap layer comprises an electrode.

13. An integrated circuit comprising:

an electrode;

a substrate including doped regions; and

a transistor including at least one dielectric layer and a transistor channel, the transistor channel located in the substrate between the doped regions, the dielectric layer separating the electrode from the transistor channel, the dielectric layer comprising:

a zirconium oxide and at least one dopant selected from the group comprising hafnium and titanium and having a first side and a second side, wherein the first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate, and wherein the dielectric layer is stressed.

14. The integrated circuit of claim 13 , comprising a memory device, wherein the transistor is configured as a selection transistor.