Integrated circuit with bit lines positioned in different planes
View Patent ↗An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.
1. An integrated circuit, comprising:
a memory cell array comprising a plurality of memory cells;
a first plurality of bit lines positioned in a first plane, the first plurality of bit lines electrically coupled to a first set of the memory cells;
a second plurality of bit lines positioned in a second plane that is different than the first plane, the second plurality of bit lines electrically coupled to a second set of the memory cells; and
wherein the first plane and the second plane are positioned at different vertical heights in the integrated circuit.
2. The integrated circuit of claim 1 , wherein each bit line in the first plurality of bit lines is positioned between two bit lines in the second plurality of bit lines, and wherein each bit line in the second plurality of bit lines is positioned between two bit lines in the first plurality of bit lines.
3. The integrated circuit of claim 1 , and further comprising:
a plurality of word lines positioned in a third plane that is different than the first plane and the second plane, the plurality of word lines electrically coupled to the memory cells.
4. The integrated circuit of claim 1 , and further comprising:
a plurality of sense amplifiers, each sense amplifier electrically coupled to two of the bit lines.
5. The integrated circuit of claim 4 , wherein each sense amplifier is electrically coupled to one bit line in the first plurality and one bit line in the second plurality.
6. The integrated circuit of claim 4 , wherein each sense amplifier is electrically coupled to two bit lines in the first plurality or two bit lines in the second plurality.
7. The integrated circuit of claim 1 , wherein the memory cell array comprises a folded bit line architecture.
8. The integrated circuit of claim 1 , wherein the memory cell array comprises an open bit line architecture.
9. The integrated circuit of claim 1 , wherein each memory cell includes a selection transistor and a storage capacitor.
10. The integrated circuit of claim 1 , wherein the integrated circuit is a dynamic random access memory (DRAM).
11. The integrated circuit of claim 1 , and further comprising:
a first plurality of vertically extending electrical contact structures configured to electrically couple the first plurality of bit lines to the first set of memory cells;
a second plurality of vertically extending electrical contact structures configured to electrically couple the second plurality of bit lines to the second set of memory cells; and
wherein the first plurality of electrical contact structures each have a different height than the second plurality of electrical contact structures.
12. The integrated circuit of claim 1 , wherein the first plurality of bit lines is arranged on a semiconductor substrate at a greater distance from the semiconductor substrate than the second plurality of bit lines and word lines of the integrated circuit, and wherein the second plurality of bit lines is arranged on the semiconductor substrate at a greater distance from the semiconductor substrate than the word lines.
13. The integrated circuit of claim 1 , wherein substantially an entire length of each bit line in the first plurality of bit lines is positioned in the first plane, and substantially an entire length of each bit line in the second plurality of bit lines is positioned in the second plane.
14. The integrated circuit of claim 1 , and further comprising:
a plurality of word lines electrically coupled to the memory cells and configured to enable access to the memory cells when the word lines are enabled; and
wherein the first and second pluralities of bit lines are configured for reading and writing data to and from the memory cells when the word lines are enabled.
15. An integrated circuit, comprising:
a substrate including a memory cell array having a plurality of memory cells;
a plurality of word lines positioned in a lateral plane on the substrate and electrically coupled to the memory cells;
a first plurality of bit lines positioned a first vertical distance above the word lines and electrically coupled to a first set of the memory cells; and
a second plurality of bit lines positioned a second vertical distance above the word lines and electrically coupled to a second set of the memory cells, wherein the second vertical distance is different than the first vertical distance.
16. The integrated circuit of claim 15 , wherein each bit line in the first plurality of bit lines is positioned between two bit lines in the second plurality of bit lines, and wherein each bit line in the second plurality of bit lines is positioned between two bit lines in the first plurality of bit lines.
17. The integrated circuit of claim 15 , and further comprising:
a plurality of sense amplifiers, each sense amplifier electrically coupled to two of the bit lines.
18. The integrated circuit of claim 15 , and further comprising:
a first plurality of vertically extending electrical contact structures configured to electrically couple the first plurality of bit lines to the first set of memory cells;
a second plurality of vertically extending electrical contact structures configured to electrically couple the second plurality of bit lines to the second set of memory cells; and
wherein the first plurality of electrical contact structures have a different height than the second plurality of electrical contact structures.
19. The integrated circuit of claim 15 , wherein substantially an entire length of each bit line in the first plurality of bit lines is positioned at the first vertical distance, and substantially an entire length of each bit line in the second plurality of bit lines is positioned at the second vertical distance.
20. A system comprising:
a host; and
a memory device communicatively coupled to the host, the memory device comprising:
an array of memory cells;
a plurality of word lines positioned in a first lateral plane, the plurality of word lines electrically coupled to the memory cells;
a first plurality of bit lines positioned in a second lateral plane, the first plurality of bit lines electrically coupled to a first set of the memory cells;
a second plurality of bit lines positioned in a third lateral plane, the second plurality of bit lines electrically coupled to a second set of the memory cells; and
wherein the first plane, the second plane, and the third plane are each positioned at different vertical heights in the memory device.