Integrated circuit with conductive structures
View Patent ↗An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
1. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines, wherein each of the transistors comprises a charge storage layer disposed in the layer of the conductive structures.
2. The integrated circuit of claim 1 , wherein the charge storage layer comprises a polysilicon layer.
3. The integrated circuit of claim 2 , wherein sections of the wordlines form control gate electrodes of each of the transistors.
4. The integrated circuit of claim 1 , wherein the conductive structures comprise a grid.
5. The integrated circuit of claim 1 , wherein the conductive structures extend parallel to a horizontal surface of a semiconductor substrate.
6. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines, wherein the conductive structures comprise conductive lines extending parallel to the wordlines.
7. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines, wherein the conductive structures have a vertical cross-section in which the conductive structures have a greater vertical dimension than horizontal dimension.
8. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
a conductive structure disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structure being insulated from the wordlines, wherein the conductive structure is embedded in an insulating liner having a U-shaped vertical cross-section.
9. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array;
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines; and
a voltage supply source configured to apply a voltage to the conductive structures.
10. An integrated circuit, comprising:
an array of transistors, wherein a plurality of the transistors are arranged in NAND strings, the strings being separated by insulating trenches;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines.
11. An integrated circuit, comprising:
an array of transistors, wherein each of the transistors comprises a charge storage layer disposed parallel to a horizontal surface of a semiconductor substrate;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array; and
conductive structures disposed in a layer beneath the wordlines and arranged between the transistors, the conductive structures being insulated from the wordlines.
12. An integrated circuit, comprising:
an array of transistors;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array;
conductive structures disposed between transistors, the conductive structures being insulated from the wordlines, wherein each of the transistors comprises a charge storage layer disposed in a layer of the conductive structures; and
an interconnection configured to connect any of the conductive structures with a fixed potential.
13. The integrated circuit of claim 12 , wherein the conductive structures are disposed in a layer beneath the wordlines.
14. The integrated circuit of claim 12 , wherein the charge storage layer comprises a polysilicon layer.
15. The integrated circuit of claim 12 , wherein sections of the wordlines form control gate electrodes of each of the transistors.
16. An integrated circuit, comprising:
an array of transistors, wherein a plurality of the transistors is arranged in NAND strings, the strings being separated by insulating trenches;
a plurality of wordlines, individual ones of the wordlines being coupled to a plurality of the transistors of the array;
conductive structures disposed between transistors, the conductive structures being insulated from the wordlines; and
an interconnection configured to connect any of the conductive structures with a fixed potential.