Integrated circuit including an array of diodes coupled to a layer of resistance changing material
View Patent ↗An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.
1. An integrated circuit comprising:
an array of diodes;
an electrode coupled to each diode;
a continuous layer of phase change material coupled to the electrodes and extending over the array of diodes; and
bit lines coupled to the continuous layer of phase change material,
wherein the continuous layer of phase change material provides a phase change element at each intersection of each electrode and each bit line.
2. The integrated circuit of claim 1 , further comprising:
an etch stop material coupling each bit line to the layer of phase change material.
3. The integrated circuit of claim 1 , wherein each phase change element is laterally surrounded by dielectric material.
4. The integrated circuit of claim 1 , further comprising:
a diffusion barrier coupling each electrode to the layer of phase change material,
wherein each electrode comprises silicon.
5. A system comprising:
a host; and
a memory device communicatively coupled to the host, the memory device comprising:
word lines;
vertical diodes coupled to each word line;
an electrode coupled to each vertical diode;
a continuous layer of phase change material coupled to the electrodes and extending over the vertical diodes; and
bit lines coupled to the continuous layer of phase change material,
wherein the continuous layer of phase change material provides a phase change element at each intersection of each word line and each bit line.
6. The system of claim 5 , wherein the memory device further comprises:
an etch stop material coupling each bit line to the layer of phase change material.
7. The system of claim 5 , wherein the memory device comprises a circuit configured to access a selected phase change element at an intersection of a selected bit line and a selected word line by:
applying a first voltage to the selected bit line with the unselected bit lines floating;
applying a second voltage to the selected word line; and
applying the first voltage to the unselected word lines,
wherein the first voltage is based on a state of a neighboring phase change element coupled to the selected word line.
8. The system of claim 5 , wherein the memory device further comprises:
a diffusion barrier coupling each electrode to the layer of phase change material,
wherein each electrode comprises silicon.