Circuit with selectable data paths
View Patent ↗A first data path is coupled between a data input and a data output of a circuit. A second data path is coupled between the data input and the data output. The first data path includes a parallelization circuit coupled to the data input to receive a serial data signal and configured to generate a parallelized data signal from the serial data signal, a first sampling circuit coupled to the parallelization circuit and configured to sample the parallelized data signal, and a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal. The second data path includes a second sampling circuit coupled to the data input and configured to sample the serial data signal. A selection circuit is configured to select between the first data path and the second data path.
1. An integrated circuit, comprising:
a data input;
a data output;
a first data path coupled between the data input and the data output, the first data path comprising:
a parallelization circuit coupled to the data input to receive a serial data signal and configured to generate a parallelized data signal from the serial data signal,
a first sampling circuit coupled to the parallelization circuit and configured to sample the parallelized data signal, and
a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal;
a second data path coupled between the data input and the data output, the second data path comprising a second sampling circuit coupled to the data input and configured to sample the serial data signal; and
a selection circuit configured to select between the first data path and the second data path.
2. The integrated circuit of claim 1 , comprising:
a memory circuit coupled to the first data path.
3. The integrated circuit of claim 1 , comprising:
a clock recovery circuit coupled to the data input and configured to generate a clock signal based on the serial data signal.
4. The integrated circuit of claim 1 , wherein the first data path and the second data path are of a differential type.
5. The integrated circuit of claim 1 , comprising:
a finite impulse response filter arranged in the second data path.
6. The integrated circuit of claim 5 , wherein the finite impulse response filter comprises the second sampling circuit.
7. The integrated circuit of claim 1 , wherein the second sampling circuit comprises a D-flip-flop.
8. The integrated circuit of claim 1 , comprising:
a buffer arranged between the data input and the second sampling circuit.
9. An integrated circuit, comprising:
a data input;
a data output;
a first data path coupled between the data input and the data output, the first data path comprising:
a parallelization circuit coupled to the data input to receive a serial data signal and configured to generate a parallelized data signal from the serial data signal,
a sampling circuit coupled to the parallelization circuit and configured sample the parallelized data signal, and
a serialization circuit coupled to the sampling circuit and configured to serialize the sampled parallelized data signal;
a second data path coupled between the data input and the data output, the second data path comprising a finite impulse response filter coupled to the data input and configured to filter the serial data signal; and
a selection circuit configured to select between the first data path and the second data path.
10. The integrated circuit of claim 9 , wherein the finite impulse response filter is arranged in the first data path and in the second data path.
11. The integrated circuit of claim 9 , wherein the finite impulse response filter is of a baud-spaced type.
12. The integrated circuit of claim 9 , wherein the finite impulse response filter is of a single-tap type.
13. The integrated circuit of claim 9 , comprising:
a buffer arranged in the second data path.
14. A memory module, comprising:
a first memory device; and
a second memory device,
wherein the first memory device comprises;
a first data path to forward a serial data signal to the second memory device,
a second data path to forward the serial data signal to the second memory device, and
a selection circuit configured to select between the first data path and the second data path,
wherein the first data path comprises:
a parallelization circuit configured to generate a parallelized data signal from the serial data signal,
a first sampling circuit coupled to the parallelization circuit and configured to sample the parallelized data signal, and
a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal, and
wherein the second data path comprises a second sampling circuit configured to sample the serial data signal.
15. The memory module of claim 14 , comprising:
a printed circuit board;
a first integrated circuit comprising the first memory device; and
a second integrated circuit comprising the second memory device.
16. The memory module of claim 14 , wherein the first data path and the second data path are of a differential type.
17. The memory module of claim 14 , wherein the first memory device comprises a finite impulse response filter arranged in the second data path and the finite impulse response filter comprises the second sampling circuit.
18. An electronic device, comprising:
a first integrated circuit; and
a second integrated circuit,
wherein the first integrated circuit comprises:
a first data path to forward a serial data signal to the second integrated circuit,
a second data path to forward the serial data signal to the second integrated circuit, and
a selection circuit configured to select between the first data path and the second data path,
wherein the first data path comprises:
a parallelization circuit configured to generate a parallelized data signal from the serial data signal,
a first sampling circuit coupled to the parallelization circuit and configured to sample a parallelized data signal, and
a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal, and
wherein the second data path comprises a second sampling circuit configured to sample the serial data signal.
19. The electronic device of claim 18 , wherein the first data path and the second data path are of a differential type.
20. The memory module of claim 18 , wherein the first integrated circuit comprises a finite impulse response filter arranged in the second data path and the finite impulse response filter comprises the second sampling circuit.
21. A method, comprising:
selectively forwarding data in an integrated circuit via a first data path or via a second data path;
wherein the forwarding via the first data path comprises:
receiving a serial data signal,
parallelizing the serial data signal to generate a parallelized data signal,
sampling the parallelized data signal, and
serializing the sampled parallelized data signal; and
wherein the forwarding via the second data path comprises:
receiving the serial data signal, and
sampling the serial data signal.
22. The method of claim 21 , comprising:
generating a sampling clock based on the serial data signal,
wherein the sampling of the serial data signal is accomplished based on the sampling clock.
23. The method of claim 21 , wherein the sampling of the serial data signal is accomplished in a finite impulse response filter.
24. The method of claim 21 , wherein the sampling of the serial data signal is accomplished in a D-flip-flop.
25. The method of claim 21 , wherein the integrated circuit comprises a memory circuit coupled to the first data path, and
wherein the serial data signal comprises memory read data, memory write data, and/or memory control data.