Integrated circuit with control circuit for performing retention test

1. An integrated circuit, comprising:

an array of memory cells;

a clock generator configured to generate a clock signal;

a control circuit configured to perform a retention test on the array of memory cells based on the clock signal, wherein a period of the clock signal defines a retention period for the retention test; and

a trim controller configured to trim the clock generator based on a user-defined value for the retention period and thereby modify the period of the clock signal.

2. The integrated circuit of claim 1 , wherein the retention test includes generating commands with the control circuit for writing data to a set of the memory cells, reading the written data from the set of memory cells, and comparing the written data with the read data to identify whether memory cells failed the retention test.

3. The integrated circuit of claim 2 , wherein the retention period represents the time duration between the writing of data to a memory cell and the reading of data from the memory cell.

4. The integrated circuit of claim 3 , wherein the retention period is the same for all memory cells in the set of memory cells.

5. The integrated circuit of claim 2 , wherein the set of memory cells includes all cells in the array of memory cells.

6. The integrated circuit of claim 1 , wherein the clock generator is configured to be automatically enabled at a beginning of the retention test.

7. The integrated circuit of claim 6 , wherein the clock generator is configured to be automatically disabled at an end of the retention test.

8. The integrated circuit of claim 1 , wherein the integrated circuit is a DRAM device.

9. The integrated circuit of claim 1 , wherein the control circuit is part of a built-in self-test (BIST) circuit.

10. A method of testing a memory device that includes an array of memory cells, comprising:

generating a clock signal within the memory device based on a predefined retention period;

internally generating commands in the memory device based on the clock signal, wherein the commands are configured to cause writing of data to a set of the memory cells, and reading the written data from the set of memory cells;

comparing with the memory device the written data and the read data to identify whether memory cells retained the written data for the retention period; and

automatically disabling generation of the clock signal at an end of the testing of the memory device.

11. The method of claim 10 , wherein the retention period represents the time duration between the writing of data to a memory cell and the reading of data from the memory cell.

12. The method of claim 11 , wherein the retention period is the same for all memory cells in the set of memory cells.

13. The method of claim 10 , wherein the set of memory cells includes all cells in the array of memory cells.

14. The method of claim 10 , wherein the retention period is defined by a user, and wherein the method further comprises:

trimming the clock signal within the memory device based on the user defined retention period.

15. The method of claim 10 , and further comprising:

automatically enabling generation of the clock signal at a beginning of the testing of the memory device.

16. A memory device, comprising:

an array of memory cells;

a variable clock generator configured to generate a variable clock signal;

a self-test circuit configured to perform a retention test on the array of memory cells based on the variable clock signal; and

a trim controller configured to modify a period of the clock signal based on a user-defined value for the retention period.

17. The memory device of claim 16 , wherein the retention test includes generating internal commands with the self-test circuit for writing data to a set of the memory cells, reading the written data from the set of memory cells, and comparing the written data with the read data to identify whether memory cells failed the retention test.