Phase change memory cell with MOSFET driven bipolar access device

1. A memory device, comprising

a bipolar junction transistor having an emitter, a base, and a collector;

a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and

a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to the base of the bipolar junction transistor,

wherein the bipolar junction transistor and the MOSFET are formed as a U-shaped semiconductor device having a first vertical projection and a second vertical projection, a gate of the MOSFET on the first vertical projection and the emitter of the bipolar junction transistor on the second vertical projection.

2. The memory device of claim 1 , further comprising:

a bit line coupled to a second side of the resistance changing memory element; and

a word line coupled to a gate of the MOSFET.

3. The memory device of claim 1 , wherein the base of bipolar junction transistor is formed in the same doping area as a source or a drain of the MOSFET.

4. The memory device of claim 1 , wherein the MOSFET is an n-channel MOSFET, and wherein the bipolar junction transistor is a PNP transistor.

5. The memory device of claim 1 , wherein the MOSFET is a p-channel MOSFET, and wherein the bipolar junction transistor is an NPN transistor.

6. A memory device, comprising:

a resistance changing memory element coupled to a first side of a U-shaped access device; wherein the U-shaped access device further comprises:

a doped first region having a first polarity;

a doped second region disposed above the first region, the doped second region having a second polarity;

a doped third region disposed above a first portion of the second region, the third region having the first polarity;

a doped fourth region disposed above the third region, the fourth region having the second polarity; and

a doped fifth region disposed above a second portion of the second region, the fifth region having the first polarity.

7. The memory device of claim 6 , further comprising:

a heavily doped sixth region disposed above the fifth region, the sixth region having the first polarity.

8. The memory device of claim 6 , wherein the first, third, and fifth regions are p-doped regions, and wherein the second and fourth regions are n-doped regions.

9. The memory device of claim 6 , further comprising:

a ground line coupled to the fourth region.

10. The memory device of claim 7 , further comprising:

a phase changing element coupled to the sixth region.

11. The memory device of claim 10 , further comprising:

a bit line coupled to the phase changing element.

12. The memory device of claim 6 , further comprising:

a word line formed near the third region, the word line isolated from the third region by a dielectric.

13. The memory device of claim 6 , further comprising:

a ground line coupled to the first region.

14. The memory device of claim 6 , wherein the first, second and fifth regions form a bipolar junction transistor; and wherein the second, third, and fourth regions and the word line form a MOSFET transistor.

15. The memory device of claim 14 , wherein the bipolar junction transistor is a PNP transistor, and wherein the MOSFET transistor is an n-channel MOSFET transistor.

16. The memory device of claim 6 , further comprising:

a word line formed near the third region and separated from the third region by a dielectric material;

a phase changing element coupled to the fifth region;

a bit line coupled to the phase change region; and

wherein, when a voltage is applied to the word line, a first current flows from the bit line to the first region through the phase change element, and a second current flows from the from the bit line to at least one ground line located above the fourth region.

17. The memory device of claim 6 , wherein the second region is lightly doped and the fourth region is heavily doped.

18. A method for fabricating an integrated circuit, comprising:

doping a first region of a substrate to have a first polarity;

lightly doping a second region of the substrate to have a second polarity, a bottom of the second region contacting a top of the first region;

doping a third region of the substrate to have the first polarity, a bottom of the third region contacting a first portion of a top of the second region;

heavily doping a fourth region to have the second polarity, a bottom of the fourth region contacting a top of the third region;

doping a fifth region of the substrate to have the first polarity, a bottom of the fifth region contacting a second portion of the top of the second region; and

heavily doping a sixth region to have the first polarity, a bottom of the sixth region contacting a top of the fifth region.

19. The method of claim 18 , further comprising:

isolating the third and fourth regions from the fifth and sixth regions.

20. The method of claim 18 , wherein fabricating the integrated circuit further comprises:

fabricating a bipolar transistor in a silicon substrate; and

fabricating a MOSFET transistor in the silicon substrate.

21. The method of claim 18 , further comprising:

fabricating a phase change element on a top of the sixth region;

fabricating a first line coupled to phase change element; and

fabricating a second line coupled to the third region.