Resistive memory cell accessed using two bit lines

1. An integrated circuit comprising:

a first bit line;

a resistance changing memory element coupled to the first bit line;

a second bit line;

a heater coupled to the second bit line; and

an access device coupled to the resistance changing memory element and the heater.

2. The integrated circuit of claim 1 , wherein the heater is configured for programming the resistance changing memory element.

3. The integrated circuit of claim 1 , wherein the heater laterally surrounds at least a portion of the resistance changing memory element.

4. The integrated circuit of claim 1 , wherein the resistance changing memory element laterally surrounds the heater.

5. The integrated circuit of claim 1 , further comprising:

a dielectric material between the resistance changing memory element and the heater.

6. The integrated circuit of claim 1 , wherein the resistance changing memory element is one of cylindrical-shaped and pipe-shaped.

7. The integrated circuit of claim 1 , wherein the heater is one of cylindrical-shaped and pipe-shaped.

8. The integrated circuit of claim 1 , wherein the resistance changing memory element comprises a phase change element.

9. A system comprising:

a host; and

a memory device communicatively coupled to the host; the memory device comprising:

a first bit line;

a phase change element coupled to the first bit line;

a second bit line;

a heater coupled to the second bit line; and

an access device coupled to the phase change element and the heater,

wherein the heater is configured for programming the phase change element.

10. The system of claim 9 , wherein the access device comprises a transistor.

11. The system of claim 9 , wherein the access device comprises a diode.

12. The system of claim 9 , further comprising:

a word line coupled to the access device.

13. The system of claim 9 , wherein the first bit line is parallel to the second bit line.

14. The system of claim 9 , further comprising:

a write circuit coupled to the second bit line, the write circuit configured to program the phase change element;

a sense circuit coupled to the first bit line, the sense circuit configured to read the phase change element; and

a controller configured to control the write circuit and the sense circuit.

15. A method for fabricating an integrated circuit, the method comprising:

providing a preprocessed wafer including an electrode;

fabricating a resistance changing element coupled to the electrode;

fabricating a heater coupled to the electrode;

fabricating a first bit line coupled to the heater; and

fabricating a second bit line coupled to the resistance changing element.

16. The method of claim 15 , wherein fabricating the resistance changing element comprises fabricating one of a cylindrical-shaped resistance changing element and a pipe-shaped resistance changing element.

17. The method of claim 15 , wherein fabricating the heater comprises fabricating one of a cylindrical-shaped heater and a pipe-shaped heater.

18. The method of claim 15 , further comprising:

fabricating a dielectric material spacer between the resistance changing element and the heater.

19. The method of claim 15 , wherein fabricating the resistance changing element comprises fabricating a phase change element.

20. A method for fabricating an integrated circuit, the method comprising:

providing a preprocessed wafer including an electrode;

depositing first dielectric material over the preprocessed wafer;

etching the first dielectric material to provide an opening exposing at least a portion of the electrode;

forming heater material on sidewalls of the opening;

forming second dielectric material on sidewalls of the heater material;

depositing phase change material over the first electrode and contacting the sidewalls of the second dielectric material;

etching portions of the first dielectric material and the heater material to expose portions of the sidewalls of the second dielectric material;

forming a first bit line contacting the heater material and sidewalls of the second dielectric material; and

forming a second bit line contacting the phase change material.

21. The method of claim 20 , further comprising:

recess etching a portion of the phase change material to provide a second opening; and

depositing a capping material in the second openings over the phase change material.

22. The method of claim 20 , wherein depositing the first dielectric material comprises depositing a first layer and a second layer different from the first layer.

23. The method of claim 20 , further comprising:

encapsulating the first bit line prior to forming the second bit line.

24. The method of claim 20 , wherein forming the first bit line comprises:

depositing a bit line material over exposed portions of the first dielectric material, the heater material, the second dielectric material, and the phase change material;

etching the bit line material to provide a line of bit line material contacting the heater material; and

recess etching the line of bit line material to expose sidewalls of the second dielectric material to provide the first bit line.

25. The method of claim 20 , wherein forming the second bit line comprises:

depositing a third dielectric material over exposed portions of the first dielectric material, the first bit line, the second dielectric material, and the phase change material;

planarizing the third dielectric material to expose the second dielectric material;

depositing a bit line material over exposed portions of the third dielectric material, the second dielectric material and the phase change material; and

etching the bit line material to provide the second bit line contacting the phase change material.