Multi-mode bus inversion method and apparatus

1. A method of performing bus inversion by an integrated circuit, comprising:

determining which of one of a plurality of bus inversion schemes supported by the integrated circuit should implement during operation of the integrated circuit;

configuring the integrated circuit to implement the determined bus inversion scheme;

storing a count value and a flag type associated with the bus inversion scheme for which the integrated circuit is configured, the count value indicating a number of bits of a data word that must be in a certain logic state for the data word to be inverted, the flag type indicating whether a bit inversion flag for the data word should be set to a logic zero or a logic one to indicate if the data word is inverted, wherein the flag type for a first one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic zero if the data word is inverted and the flag type for a second one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic one if the data word is inverted so that the integrated circuit accommodates bus inversion schemes having different count values and different flag types; and

processing information input to and output from the integrated circuit in accordance with the count value and the flag type associated with the bus inversion scheme for which the integrated circuit is configured.

2. The method of claim 1 , wherein configuring the integrated circuit to implement one of the bus inversion schemes comprises configuring the integrated circuit to implement the bus inversion scheme corresponding to hard-wired bus inversion configuration information obtained by the integrated circuit.

3. The method of claim 1 , wherein configuring the integrated circuit to implement one of the bus inversion schemes comprises configuring the integrated circuit to implement the bus inversion scheme corresponding to programmable bus inversion configuration information obtained by the integrated circuit.

4. The method of claim 1 , wherein configuring the integrated circuit to implement one of the bus inversion schemes comprises setting one or more register bits or latches to indicate which one of the bus inversion schemes the integrated circuit is configured to implement.

5. The method of claim 1 , wherein configuring the integrated circuit to implement one of the bus inversion schemes comprises:

selecting one of a plurality of bit count values for use by the integrated circuit in determining when bus inversion is to be implemented; and

selecting one of a plurality of flag types for use by the integrated circuit in indicating when bus inversion has been implemented, a first one of the plurality of flag types indicating the bit inversion flag should be set to a logic zero if the data word is inverted and a second one of the plurality of flag types indicating the bit inversion flag should be set to a logic one if the data word is inverted.

6. The method of claim 5 , wherein processing information input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured comprises:

inverting the data word responsive to the data word having a total number of logic zero bits exceeding the selected bit count value;

setting the bit inversion flag in accordance with the selected flag type responsive to the word being inverted; and

inverting a new data word input to the integrated circuit responsive to an input flag received by the integrated circuit being set in accordance with the selected flag type.

7. The method of claim 1 , further comprising re-configuring the integrated circuit to implement a different one of the bus inversion schemes responsive to the integrated circuit being directed to change bus inversion schemes.

8. An integrated circuit, comprising circuitry operable to:

determine which of one of a plurality of bus inversion schemes supported by the integrated circuit should implement during operation of the integrated circuit;

configure the integrated circuit to implement the determined bus inversion scheme;

store a count value and a flag type associated with the bus inversion scheme for which the integrated circuit is configured, the count value indicating a number of bits of a data word that must be in a certain logic state for the data word to be inverted, the flag type indicating whether a bit inversion flag for the data word should be set to a logic zero or a logic one to indicate if the data word is inverted, wherein the flag type for a first one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic zero to indicate the data word is inverted and the flag type for a second one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic one to indicate the data word is inverted so that the integrated circuit accommodates bus inversion schemes having different count values and different flag types; and

process information input to and output from the integrated circuit in accordance with the count value and the flag type associated with the bus inversion scheme for which the integrated circuit is configured.

9. The integrated circuit of claim 8 , wherein the circuitry is operable to implement the bus inversion scheme corresponding to hard-wired bus inversion configuration information obtained by the integrated circuit.

10. The integrated circuit of claim 8 , wherein the circuitry is operable to implement the bus inversion scheme corresponding to programmable bus inversion configuration information obtained by the integrated circuit.

11. The integrated circuit of claim 8 , wherein the circuitry comprises one or more register bits or latches operable to indicate which one of the bus inversion schemes the integrated circuit is configured to implement.

12. The integrated circuit of claim 8 , wherein the circuitry is operable to:

select one of a plurality of bit count values for use by the integrated circuit in determining when bus inversion is to be implemented; and

select one of a plurality of flag types for use by the integrated circuit in indicating when bus inversion has been implemented, a first one of the plurality of flag types indicating the bit inversion flag should be set to a logic zero if the data word is inverted and a second one of the plurality of flag types indicating the bit inversion flag should be set to a logic one if the data word is inverted.

13. The integrated circuit of claim 12 , wherein the circuitry is operable to:

invert the data word responsive to the data word having a total number of logic zero bits exceeding the selected bit count value;

set the bit inversion flag in accordance with the selected flag type responsive to the word being inverted; and

invert a new data word input to the integrated circuit responsive to an input flag received by the integrated circuit being set in accordance with the selected flag type.

14. The integrated circuit of claim 8 , wherein the circuitry is further operable to re-configure the integrated circuit to implement a different one of the bus inversion schemes responsive to the integrated circuit being directed to change bus inversion schemes.

15. An integrated circuit, comprising:

logic operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes supported by the integrated circuit, and store a count value and a flag type associated with the bus inversion scheme for which the integrated circuit is configured, the count value indicating a number of bits of a data word that must be in a certain logic state for the data word to be inverted, the flag type indicating whether a bit inversion flag for the data word should be set to a logic zero or a logic one to indicate if the data word is inverted, wherein the flag type for a first one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic zero to indicate the data word is inverted and the flag type for a second one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic one to indicate the data word is inverted so that the integrated circuit accommodates bus inversion schemes having different count values and different flag types;

a first component operable to determine whether to invert data written to the integrated circuit based on a comparison of the flag type associated with the bus inversion scheme for which the integrated circuit is configured and a flag input provided with the data written to the integrated circuit; and

a second component operable to determine whether to invert data read from the integrated circuit based on the count value and the flag type associated with the bus inversion scheme for which the integrated circuit is configured.

16. The integrated circuit of claim 15 , wherein the logic comprises one or more register bits or latches operable to store the count value and the flag type associated with the bus inversion scheme for which the integrated circuit is configured.

17. A system comprising a memory device configured to:

implement one of a plurality of bus inversion schemes supported by the memory device,

store a count value and a flag type associated with the bus inversion scheme for which the memory device is configured, the count value indicating a number of bits of a data word that must be in a certain logic state for the data word to be inverted, the flag type indicating whether a bit inversion flag for the data word should be set to a logic zero or a logic one to indicate if the data word is inverted, wherein the flag type for a first one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic zero to indicate the data word is inverted and the flag type for a second one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic one to indicate the data word is inverted so that the memory device accommodates bus inversion schemes having different count values and different flag types; and

process data written to and read from the memory device in accordance with the count value and the flag type associated with the bus inversion scheme for which the memory device is configured.