Integrated circuit having a magnetic tunnel junction device and method
View Patent ↗An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite.
1. An integrated circuit comprising:
a magnetic tunnel junction, the magnetic tunnel junction including a barrier layer, the barrier layer including carbon,
wherein the magnetic tunnel junction has a magnetoresistance ratio greater than 75%.
2. The integrated circuit of claim 1 , wherein the barrier layer comprises pyrolytic carbon.
3. The integrated circuit of claim 1 , wherein the barrier layer comprises graphene.
4. The integrated circuit of claim 1 , wherein the barrier layer comprises graphite.
5. The integrated circuit of claim 1 , wherein the barrier layer is disposed between a first ferromagnetic layer and a second ferromagnetic layer.
6. The integrated circuit of claim 5 , wherein the second ferromagnetic layer comprises a magnetization orientation selected by the application of a write current through the magnetic tunnel junction.
7. The integrated circuit of claim 6 , wherein the write current comprises a spin polarized write current determining the magnetization orientation of the second ferromagnetic layer.
8. The integrated circuit of claim 6 , wherein the barrier layer is configured to heat the magnetic tunnel junction when the write current is applied to the magnetic tunnel junction.
9. The integrated circuit of claim 5 , wherein the first ferromagnetic layer having has a fixed magnetization orientation.
10. The integrated circuit of claim 5 , comprising:
a first antiferromagnetic layer disposed proximate to the first ferromagnetic layer, the first antiferromagnetic layer being configured to pin the orientation of the first ferromagnetic layer.
11. The integrated circuit of claim 5 , comprising:
a second antiferromagnetic layer disposed proximate to the second ferromagnetic layer, the second antiferromagnetic layer being configured to pin the orientation of the second ferromagnetic layer.
12. The integrated circuit of claim 10 , wherein the first ferromagnetic layer comprises a third ferromagnetic layer disposed proximate to the first antiferromagnetic layer, a non-magnetic layer disposed proximate to the third ferromagnetic layer and a fourth ferromagnetic layer disposed proximate to the non-magnetic layer.
13. A memory module, comprising:
a plurality of integrated circuits, wherein at least one integrated circuit includes a magnetic tunnel junction, the magnetic tunnel junction including a barrier layer, the barrier layer including carbon,
wherein the magnetic tunnel junction has a magnetoresistance ratio greater than 75%.
14. The memory module of claim 13 , wherein the barrier layer comprises pyrolytic carbon.
15. The memory module of claim 13 , wherein the barrier layer comprises graphene.
16. The memory module of claim 13 , wherein at least some of the integrated circuits are stacked one above the other.
17. The integrated circuit of claim 1 , wherein the magnetic tunnel junction has a resistance times area value of 0.1Ω(μm) 2 .
18. The integrated circuit of claim 1 , wherein the barrier layer has a thickness of 5 nm.
19. The integrated circuit of claim 1 , wherein the magnetic tunnel junction is configured to withstand current densities greater than 100 MA/(cm) 2 .
20. The memory module of claim 13 , wherein the magnetic tunnel junction has a resistance times area value of 0.1Ω(μm) 2 .
21. The memory module of claim 13 , wherein the barrier layer has a thickness of 5 nm.
22. The memory module of claim 13 , wherein the magnetic tunnel junction is configured to withstand current densities greater than 100 MA/(cm) 2 .