IP Library Granted Patent US 8,093,696
Granted Patent B2
US 8,093,696 · App. 12/122,215 · Granted Jan 10, 2012

Semiconductor device

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Quick Facts
Patent No.
US 8,093,696
App. No.
12/122,215
Granted
Jan 10, 2012
Kind
B2
Abstract

According to one embodiment of the present invention, a semiconductor device is provided, that includes a semiconductor carrier; a cavity formed within the semiconductor carrier, the cavity extending from the top surface of the semiconductor carrier into the semiconductor carrier; and at least one semiconductor chip provided within the cavity.

Claims (19)

1. A semiconductor device, comprising:

a semiconductor carrier,

a cavity formed within the semiconductor carrier, the cavity extending from a top surface of the semiconductor carrier into the semiconductor carrier, and

at least one semiconductor chip provided within the cavity,

wherein the vertical position of the top surface of the at least one semiconductor chip provided within the cavity is lower than the vertical position of the top surface of the semiconductor carrier,

wherein the at least one semiconductor chip comprises vias extending through the at least one semiconductor chip,

wherein the semiconductor carrier comprises vias extending through the semiconductor carrier, and

wherein vias of a carrier substrate are connected to the vias of the at least one semiconductor chip.

2. The semiconductor device according to claim 1 , wherein the vias extending through the semiconductor carrier are formed by contact holes that are completely filled with conductive material.

3. The semiconductor device according to claim 1 , wherein the vias extending through the semiconductor carrier are formed by contact holes and a layer of conductive material that covers a side surface of the contact holes.

4. The semiconductor device according to claim 1 , wherein the at least one semiconductor chip comprises a stack of semiconductor chips, wherein the semiconductor chips comprise vias that extend through the semiconductor chips, ends of the vias of different semiconductor chips which face each other being electrically connected with each other.

5. The semiconductor device according to claim 1 , wherein the at least one semiconductor chip is attached to a bottom surface of the cavity by an adhesive layer.

6. The semiconductor device according to claim 5 , wherein the adhesive layer comprises a solder material layer.

7. The semiconductor device according to claim 5 , wherein the adhesive layer comprises an epoxy layer.

8. The semiconductor device according to claim 5 , wherein the adhesive layer comprises a tape layer.

9. The semiconductor device according to claim 5 , wherein the adhesive layer has a thickness ranging between 5 μm and 100 μm.

10. The semiconductor device according to claim 5 , wherein the adhesive layer has a high thermal conductivity.

11. The semiconductor device according to claim 1 , wherein the cavity has a depth that ranges between 60 μm and 500 μm.

12. The semiconductor device according to claim 11 , wherein a thickness of parts of the semiconductor carrier located below the cavity is less than 200 μm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036575/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2008
From: YOON, KIMYUNG; DOBRITZ, STEPHAN; RUCKMICH, STEFAN
To: QIMONDA AG
Reel/Frame 021231/0173 →