Packaging systems and methods
View Patent ↗Packaging systems and methods for semiconductor devices are disclosed. In one embodiment, a packaging system includes a first plate having a first coefficient of thermal expansion (CTE). An integrated circuit is mountable to the first plate. The packaging system includes a second plate coupleable over the first plate over the integrated circuit. The second plate has a second CTE that is substantially a same CTE as the first CTE. A plurality of solder balls is coupleable to the first plate or the second plate and to the integrated circuit.
1. A packaging system for an integrated circuit, comprising:
a first plate having a first coefficient of thermal expansion;
a first buffer layer disposed between an upper side of the first plate and a lower side of the integrated circuit;
thin film wiring mounted on the first plate and adapted to pass directly through the first buffer layer to couple bond pads on the lower side of the integrated circuit to associated solder balls mounted on a lower side of the first plate;
a second buffer layer disposed directly above an upper side of the integrated circuit; and
a second plate mounted directly over the second buffer layer, the second plate having a second coefficient of thermal expansion, the second coefficient of thermal expansion being substantially the same as the first coefficient of thermal expansion.
2. The packaging system according to claim 1 , wherein the first buffer layer has a third coefficient of thermal expansion, wherein the second buffer layer has a fourth coefficient of thermal expansion, the fourth coefficient of thermal expansion being substantially the same as the third coefficient of thermal expansion.
3. The packaging system according to claim 1 , wherein the first buffer layer has a predetermined first thickness, the second buffer layer has a predetermined second thickness, and the first thickness and the second thickness are substantially equal.
4. The packaging system according to claim 1 , wherein the first buffer layer or the second buffer layer comprise an adhesive, tape, silicone, polyimide, Elastosil™, epoxy, elastic polymer, or a combination thereof.
5. The packaging system according to claim 1 , wherein the first plate or the second plate comprise a semiconductor substrate or a printed circuit board substrate.
6. The packaging system according to claim 1 , wherein the first plate or the second plate comprise a polymer, a metal, or a silicon-enriched mold compound.
7. The packaging system according to claim 1 , wherein the first plate has a predetermined first thickness, wherein the second plate has a predetermined second thickness, and the first thickness and the second thickness are substantially equal.
8. The packaging system according to claim 1 , wherein the packaging system comprises a ball grid array package, a land grid array package, or a wafer level package.
9. A semiconductor device, comprising:
a first plate, the first plate comprising a first coefficient of thermal expansion;
a first buffer layer disposed over the first plate;
at least one integrated circuit disposed over the first buffer layer;
a second buffer layer disposed directly over the at least one integrated circuit;
a second plate disposed directly over the second buffer layer, the second plate comprising a second coefficient of thermal expansion, the second coefficient of thermal expansion being substantially the same as the first coefficient of thermal expansion; and
thin film wiring mounted on the first plate and adapted to pass directly through the first buffer layer to couple bond pads on a lower side of the at least one integrated circuit to associated solder balls mounted on a lower side of the first plate.
10. The semiconductor device according to claim 9 , wherein the at least one integrated circuit comprises a plurality of integrated circuits and wherein at least two of the plurality of integrated circuits are electrically coupled by the thin film wiring.
11. The semiconductor device according to claim 9 , wherein the solder balls are partially embedded in the first plate.
12. The semiconductor device according to claim 9 , wherein the solder balls are embedded in the first plate by about 30% or greater.
13. The semiconductor device according to claim 9 , wherein the first plate has a first Young's modulus, wherein the second plate has a second Young's modulus, wherein the second Young's modulus is substantially equal to the first Young's modulus.
14. The semiconductor device according to claim 9 , wherein at least one of the first plate or the second plate includes a plurality of through-hole vias adapted to couple the at least one integrated circuit to associated bond pads on an external surface of the first plate or the second plate.